Cypress CY7C68034 Manual De Usuario

Document #: 001-04247 Rev. *D

Page 31 of 33

The following recommendations should be followed to ensure
reliable high-performance operation:

• At least a four-layer impedance controlled boards is recom-

mended to maintain signal quality.

• Specify impedance targets (ask your board vendor what 

they can achieve) to meet USB specifications.

• To control impedance, maintain trace widths and trace 

spacing.

• Minimize any stubs to avoid reflected signals.

• Connections between the USB connector shell and signal 

ground must be done near the USB connector.

• Bypass/flyback caps on VBUS, near connector, are recom-

mended.

• DPLUS and DMINUS trace lengths should be kept to within 

2 mm of each other in length, with preferred length of 
20–30 mm.

• Maintain a solid ground plane under the DPLUS and 

DMINUS traces. Do not allow the plane to be split under 
these traces.

• No vias should be placed on the DPLUS or DMINUS trace 

routing unless absolutely necessary.

• Isolate the DPLUS and DMINUS traces from all other signal 

traces as much as possible.

Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the

heat transfer area below the package to provide a good
thermal bond to the circuit board. A Copper (Cu) fill is to be
designed into the PCB as a thermal pad under the package.
Heat is transferred from the NX2LP-Flex to the PCB through
the device’s metal paddle on the bottom side of the package.
It is then conducted from the PCB’s thermal pad to the inner
ground plane by a 5 x 5 array of vias. A via is a plated through
hole in the PCB with a finished diameter of 13 mil. The QFN’s
metal die paddle must be soldered to the PCB’s thermal pad.
Solder mask is placed on the board top side over each via to
resist solder flow into the via. The mask on the top side also
minimizes outgassing during the solder reflow process.

For further information on this package design please refer to
the application note Surface Mount Assembly of AMKOR’s
MicroLeadFrame (MLF) Technology. This application note can
be downloaded from AMKOR’s website from the following
URL:

. 

The application note provides detailed information on board
mounting guidelines, soldering flow, rework process, etc.

Figure 21 below displays a cross-sectional area underneath
the package. The cross section is of only one via. The solder
paste template needs to be designed to allow at least 50%
solder coverage. The thickness of the solder paste template
should be 5 mil. It is recommended that ‘No Clean’ type 3
solder paste is used for mounting the part. Nitrogen purge is
recommended during reflow. 

Figure 22 is a plot of the solder mask pattern and Figure 23
displays an X-Ray image of the assembly (darker areas
indicate solder)

16. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High 

Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.

0.017” dia

0.013” dia

Via hole for thermally connecting the

QFN to the circuit board ground plane.

This figure only shows the top three layers of the 

circuit board: Top Solder, PCB Dielectric, and the Ground Plane.