Cypress CY7C1163V18 Manual De Usuario

Document Number: 001-06582 Rev. *D

Page 20 of 29

During power up, when the DOFF is tied HIGH, the DLL gets
locked after 2048 cycles of stable clock. QDR-II+ SRAMs must
be powered up and initialized in a predefined manner to prevent
undefined operations. 

■

Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)

❐

Apply V

DD

 before V

DDQ

❐

Apply V

DDQ 

before V

REF

 or at the same time as V

REF

■

Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL

■

DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t

KC Var

■

The DLL functions at frequencies down to 120 MHz

■

If the input clock is unstable and the DLL is enabled, then the
DLL locks onto an incorrect frequency, causing unstable SRAM
behavior. To avoid this, provide 2048 cycles stable clock to
relock to the desired clock frequency

K

K

Fix HIGH (tie to VDDQ)

VDD/VDDQ

DOFF

Clock Start (Clock Starts after VDD/VDDQ is Stable)

Unstable Clock

> 2048 Stable Clock

Start Normal 
Operation

VDD/VDDQ Stable (< + 0.1V DC per 50 ns)