Cypress CY62158EV30 Manual De Usuario
8-Mbit (1024K x 8) Static RAM
CY62158EV30 MoBL
®
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05578 Rev. *D
Revised April 19, 2007
Features
• Very high speed: 45 ns
— Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62158DV30
• Ultra low standby power
• Ultra low standby power
— Typical standby current: 2
µA
— Maximum standby current: 8
µA
• Ultra low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Easy memory expansion with CE
1
, CE
2
, and OE features
• Automatic power down when deselected
• CMOS for optimum speed/power
• Offered in Pb-free 48-ball VFBGA, 44-pin TSOP II and
• CMOS for optimum speed/power
• Offered in Pb-free 48-ball VFBGA, 44-pin TSOP II and
48-pin TSOP I packages
Functional Description
The CY62158EV30 is a high performance CMOS static RAM
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption. Placing the device into standby
mode reduces power consumption significantly when
deselected (CE
1
HIGH or CE
2
LOW). The eight input and
output pins (IO
0
through IO
7
) are placed in a high impedance
state when the device is deselected (CE
1
HIGH or CE
2
LOW),
the outputs are disabled (OE HIGH), or a write operation is in
progress (CE
1
LOW and CE
2
HIGH and WE LOW).
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. Data on the eight
IO pins (IO
0
through IO
7
) is then written into the location
specified on the address pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and
CE
2
HIGH) and OE LOW while forcing the WE HIGH. Under
these conditions, the contents of the memory location
specified by the address pins appear on the IO pins. See the
for a complete description of read and
write modes.
Logic Block Diagram
A0
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
WE
OE
A
13
A
14
A
15
A
16
ROW DECODER
COLUMN DECODER
1024K x 8
ARRAY
DATA IN DRIVERS
A10
A11
A
17
CE1
CE2
A12
A
18
A
19
Notes