Cypress CY7C65113C Manual De Usuario
CY7C65113C
Document #: 38-08002 Rev. *D
Page 17 of 49
9.0
General-purpose I/O Ports
There are 11 GPIO pins (P0[7:0] and P1[2:0]) for the hardware interface. Each port can be configured as inputs with internal
pull-ups, open drain outputs, or traditional CMOS outputs. The data for each GPIO port is accessible through the data registers.
Special care should be taken with any unused GPIO data bits. An unused GPIO data bit, either a pin on the chip or a port bit that
is not bonded on a particular package, must not be left floating when the device enters the suspend state. If a GPIO data bit is
left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB
Specifications. If a ‘1’ is written to the unused data bit and the port is configured with open drain outputs, the unused data bit
remains in an indeterminate state. Therefore, if an unused port bit is programmed in open-drain mode, it must be written with a ‘0.’
A read from a GPIO port always returns the present state of the voltage at the pin, independent of the settings in the Port Data
A read from a GPIO port always returns the present state of the voltage at the pin, independent of the settings in the Port Data
Registers. During reset, all of the GPIO pins are set to a high-impedance input state. Writing a ‘0’ to a GPIO pin drives the pin
LOW. In this state, a ‘0’ is always read on that GPIO pin unless an external source overdrives the internal pull-down device.
Figure 9-1. Block Diagram of a GPIO Pin
Port 0 Data
Address 0x00
Bit #
7
6
5
4
3
2
1
0
Bit Name
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Figure 9-2. Port 0 Data
Port 1 Data
Address 0x01
Bit #
-
-
-
-
-
2
1
0
Bit Name
-
-
-
-
-
P1.2
P1.1
P1.0
Read/Write
-
-
-
-
-
R/W
R/W
R/W
Reset
-
-
-
-
-
1
1
1
Figure 9-3. Port1 Data
GPIO
V
CC
14 k
Ω
GPIO
CFG
mode
2-bits
Data
Out
Latch
Internal
Data Bus
Port Read
Port Write
Interrupt
Enable
Cont
rol
Cont
ro
l
Interrupt
Controller
Q1
Q3*
Q2
*Port 0,1: Low I
sink
Data
Interrupt
Latch
OE
Reg_Bit
STRB
Data
In
Latch
In
Latch
(Latch is Transparent)
PIN