Cypress CY7C65113C Manual De Usuario

Document #: 38-08002  Rev. *D

Page 21 of 49

The I2C-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and

multi-master modes of operation. The I2C-compatible block functions by handling the low-level signaling in hardware, and issuing

interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the

hardware keeps the I2C-compatible bus idle if necessary.
The I2C-compatible block generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a

stop bit is detected by the slave when in receive mode, or when arbitration is lost. Details of the interrupt responses are given in

Section 14.8. 
The I2C-compatible interface consists of two registers, an I

2

C Data Register (Figure 12-1) and an I

2

C Status and Control Register

(Figure 12-2). The I

2

C Data Register is implemented as separate read and write registers. Generally, the I

2

C Status and Control

Register should only be monitored after the I

2

C interrupt, as all bits are valid at that time. Polling this register at other times could

read misleading bit status if a transaction is underway.
The I

2

C clock (SCL) is connected to bit 0 of GPIO port 1, and the I

2

C SDA data is connected to bit 1 GPIO port 1. The port

selection is determined by settings in the I

2

C Port Configuration Register (Section 11.0). Once the I

2

C-compatible functionality is

enabled by setting the I

2

C Enable bit of the I

2

C Status and Control Register (bit 0, Figure 12-2), the two LSB ([1:0]) of the

corresponding GPIO port is placed in Open Drain mode, regardless of the settings of the GPIO Configuration Register. In Open

Drain mode, the GPIO pin outputs LOW if the pin’s Data Register is ‘0’, and the pin is in Hi-Z mode if the pin’s Data Register is

‘1’. The electrical characteristics of the I

2

C-compatible interface is the same as that of GPIO port 1. Note that the I

OL 

(max) is 2

mA @ V

OL 

= 2.0V for port 1.

All control of the I

2

C clock (SCL) and data (SDA) lines is performed by the I

2

C-compatible block. 

Bits [7..0]: I

2

C Data

Contains the 8-bit data on the I

2

C Bus. 

The I

2

C Status and Control register bits are defined in Table 12-1, with a more detailed description following. 

Bit  #

7

6

5

4

3

2

1

0

Bit Name

 I

2

C Data 7

 I

2

C Data 6

 I

2

C Data 5

 I

2

C Data 4

 I

2

C Data 3

 I

2

C Data 2

 I

2

C Data 1

 I

2

C Data 0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

X

X

X

X

X

X

X

X

Bit  #

7

6

5

4

3

2

1

0

Bit Name

MSTR Mode Continue/Bu

sy

Xmit Mode

ACK

Addr

ARB 

Lost/Restart

Received 

Stop

I

2

C Enable

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

I

2

C Enable

When set to ‘1’, the I

2

C-compatible function is enabled. When cleared, I

2

C GPIO pins operate 

normally.

1

Received Stop

Reads 1 only in slave receive mode, when I

2

C Stop bit detected (unless firmware did not ACK the 

last transaction).

2

ARB Lost/Restart Reads 1 to indicate master has lost arbitration. Reads 0 otherwise. 

Write to 1 in master mode to perform a restart sequence (also set Continue bit).

3

Addr

Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration.

Reads 0 otherwise. This bit should always be written as 0.

4

ACK

In receive mode, write 1 to generate ACK, 0 for no ACK.

In transmit mode, reads 1 if ACK was received, 0 if no ACK received.

5

Xmit Mode

Write to 1 for transmit mode, 0 for receive mode.