Cypress CY7C65113C Manual De Usuario
CY7C65113C
Document #: 38-08002 Rev. *D
Page 8 of 49
4.0
Product Summary Tables
4.1
Pin Assignments
3.0
Pin Configurations
Table 4-1. Pin Assignments
Name
I/O
28-pin
Description
D+[0], D–[0]
I/O
5, 6
Upstream port, USB differential data.
D+[1], D–[1]
I/O
7, 8
Downstream Port 1, USB differential data.
D+[2], D–[2]
I/O
9, 10
Downstream Port 2, USB differential data.
D+[3], D–[3]
I/O
23, 24
Downstream Port 3, USB differential data.
D+[4], D–[4]
I/O
21, 22
Downstream Port 4, USB differential data.
P0
I/O
P1[7:0]
11, 15, 12, 16, 13, 17, 14, 18
GPIO Port 0 capable of sinking 7 mA (typical).
P1
I/O
P1[2:0]
25, 27, 26
GPIO Port 1 capable of sinking 7 mA (typical).
XTAL
IN
IN
2
6-MHz crystal or external clock input.
XTAL
OUT
OUT
1
6-MHz crystal out.
V
PP
19
Programming voltage supply, tie to ground during normal operation.
V
CC
28
Voltage supply.
GND
4, 20
Ground.
V
REF
IN
3
External 3.3V supply voltage for the downstream differential data output
buffers and the D+ pull-up.
1
2
3
4
5
6
7
9
11
12
13
14
XTALIN
10
8
15
17
16
19
18
21
20
23
22
25
24
26
28
27
V
CC
P1[1]
P1[0]
P1[2]
D–[3]
D+[3]
D–[4]
D+[4]
V
REF
GND
D+[0]
D–[0]
D+[1]
D–[1]
D+[2]
D–[2]
P0[7]
P0[5]
P0[3]
P0[1]
XTALOUT
GND
V
PP
P0[0]
P0[2]
P0[4]
P0[6]
CY7C65113C
28-pin SOIC
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