Cypress CY7C1334H Manual De Usuario
CY7C1334H
Document #: 38-05678 Rev. *B
Page 13 of 13
Document History Page
Document Title: CY7C1334H 2-Mbit (64K x 32) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05678
Document Number: 38-05678
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
347357
See ECN
PCI
New Data Sheet
*A
424820
See ECN
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from V
“3901 North First Street” to “198 Champion Court”
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from V
DDQ
< V
DD
to
V
DDQ
< V
DD
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Replaced Package Diagram of 51-85050 from *A to *B
Information table.
Replaced Package Diagram of 51-85050 from *A to *B
*B
459347
See ECN
NXR
Converted from Preliminary to Final
Included 2.5V I/O option
Updated the Ordering Information table.
Included 2.5V I/O option
Updated the Ordering Information table.