Cypress CY62147DV18 Manual De Usuario
4-Mb (256K x 16) Static RAM
CY62147DV18
MoBL2™
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Document #: 38-05343 Rev. *B
Revised February 26, 2004
Features
• Very high speed: 55 ns and 70 ns
• Wide voltage range: 1.65V – 2.25V
• Pin-compatible with CY62147CV18
• Ultra-low active power
• Wide voltage range: 1.65V – 2.25V
• Pin-compatible with CY62147CV18
• Ultra-low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 6 mA @ f = f
— Typical active current: 6 mA @ f = f
max
• Ultra low standby power
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered 48-ball BGA
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered 48-ball BGA
Functional Description
[1]
The CY62147DV18 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
mode reducing power consumption by more than 99% when
deselected (CE HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O
0
through I/O
15
) are placed in a high-im-
pedance state when: deselected (CE HIGH), outputs are dis-
abled (OE HIGH), both Byte High Enable and Byte Low Enable
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by asserting Chip En-
Writing to the device is accomplished by asserting Chip En-
able (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O
0
through
I/O
7
), is written into the location specified on the address pins
(A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by asserting Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table for a complete description of read and write
modes.
The CY62147DV18 is available in a 48-ball FBGA package.
The CY62147DV18 is available in a 48-ball FBGA package.
Note:
1.
For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
256K x 16
RAM Array
I/O
0
– I/O
7
ROW
DEC
O
DE
R
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SE
NS
E A
M
PS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
– I/O
15
CE
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
Power
-
Down
Circuit
A
10