Cypress CY7C1380D Manual De Usuario

Document #: 38-05543 Rev. *F

Page 12 of 34

The CY7C1380D/CY7C1382D incorporates a serial boundary

scan test access port (TAP).This part is fully compliant with

1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V

I/O logic levels.
The CY7C1380D/CY7C1382D contains a TAP controller,

instruction register, boundary scan register, bypass register, and

ID register.

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(V

SS

) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V

DD 

through a pull up resistor. TDO must be left

unconnected. Upon power up, the device comes up in a reset

state which does not interfere with the operation of the device.

The 0 or 1 next to each state represents the value of TMS at the

rising edge of TCK.

Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are

captured on the rising edge of TCK. All outputs are driven from

the falling edge of TCK.

Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. This pin may be left

unconnected if the TAP is not used. The ball is pulled up

internally, resulting in a logic HIGH level.

Test Data-In (TDI)
The TDI ball is used to serially input information into the registers

and can be connected to the input of any of the registers. The

register between TDI and TDO is chosen by the instruction that

is loaded into the TAP instruction register. TDI is internally pulled

up and can be unconnected if the TAP is unused in an appli-

cation. TDI is connected to the most significant bit (MSB) of any

register. (See 

.)

Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current state

of the TAP state machine. The output changes on the falling edge

of TCK. TDO is connected to the least significant bit (LSB) of any

register. (See 

A Reset is performed by forcing TMS HIGH (V

DD

) for five rising

edges of TCK. This Reset does not affect the operation of the

SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO

comes up in a High-Z state.

Registers are connected between the TDI and TDO balls and

enable data to be scanned in and out of the SRAM test circuitry.

Only one register can be selected at a time through the

instruction register. Data is serially loaded into the TDI ball on the

rising edge of TCK. Data is output on the TDO ball on the falling

edge of TCK.

Instruction Register
Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the TDI

and TDO balls as shown in the 

.

Upon power up, the instruction register is loaded with the

IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as described

in the previous section.

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

1

1

1

0

1

1

0

0

1

1

1

0

0

0

0

0

0

0

0

0

1

0

1

1

0

1

0

1

1

1

1

0

Bypass Register

0

Instruction Register

0

1

2

Identification Register

0

1

2

29

30

31

.

.

.

Boundary Scan Register

0

1

2

.

.

x

.

.

.

    S

election

    Circuitr

y

Selection

Circuitry

TCK

TMS

TAP CONTROLLER

TDI

TDO