Cypress CY62167E MoBL Manual De Usuario
16-Mbit (1M x 16 / 2M x 8) Static RAM
CY62167E MoBL
®
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-15607 Rev. *A
Revised June 07, 2007
Features
• Configurable as 1M x 16 or as 2M x 8 SRAM
• Very high speed: 45 ns
• Wide voltage range: 4.5V–5.5V
• Ultra low standby power
• Very high speed: 45 ns
• Wide voltage range: 4.5V–5.5V
• Ultra low standby power
— Typical standby current: 1.5
µA
— Maximum standby current: 12
µA
• Ultra low active power
— Typical active current: 2.2 mA @ f = 1 MHz
• Easy memory expansion with CE
1
, CE
2
, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Offered in 48-pin TSOP I package
• CMOS for optimum speed and power
• Offered in 48-pin TSOP I package
Functional Description
The CY62167E is a high performance CMOS static RAM
organized as 1M words by 16 bits/2M words by 8 bits. This
device features advanced circuit design to provide an ultra low
active current. This is ideal for providing More Battery Life
™
(MoBL
®
) in portable applications such as cellular telephones.
The device also has an automatic power down feature that
reduces power consumption by 99% when addresses are not
toggling. Place the device into standby mode when deselected
(CE
1
HIGH, or CE
2
LOW, or both BHE and BLE are HIGH).
The input and output pins (IO
0
through IO
15
) are placed in a
high impedance state when:
• The device is deselected (CE
1
HIGH or CE
2
LOW)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH) or
• A write operation is in progress (CE
1
LOW, CE
2
HIGH, and
WE LOW)
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO
0
through IO
7
), is
written into the location specified on the address pins (A
0
through A
19
). If Byte High Enable (BHE) is LOW, then data
from the IO pins (IO
8
through IO
15
) is written into the location
specified on the address pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and
CE
2
HIGH) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins appears on IO
0
to IO
7
. If Byte High Enable (BHE) is LOW,
then data from memory appears on IO
8
to IO
15
. See the
for a complete description of read and write
modes.
Logic Block Diagram
1M × 16 / 2M x 8
RAM ARRAY
IO
0
–IO
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO
8
–IO
15
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
A
18
A
10
POWER DOWN
CIRCUIT
BHE
BLE
BLE
CE
2
CE
1
CE
2
CE
1
BYTE
A
19
Note
.