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Cypress CY8C24094 Manual De Usuario

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CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. *M
Page 10 of 47
8.1  68-Pin Part Pinout 
The 68-pin QFN part table and drawing below is for the CY8C24994 PSoC device.
Table 8-3.  68-Pin Part Pinout (QFN
)
Pin 
No.
Type
Name
Description
Figure 8-3.  CY8C24994 68-Pin PSoC Device
Digital Analog
1
I/O
M
P4[7]
2
I/O
M
P4[5]
3
I/O
M
P4[3]
4
I/O
M
P4[1]
5
NC
No connection.
6
NC
No connection.
7
Power
Vss
Ground connection.
8
I/O
M
P3[7]
9
I/O
M
P3[5]
10
I/O
M
P3[3]
11
I/O
M
P3[1]
12
I/O
M
P5[7]
13
I/O
M
P5[5]
14
I/O
M
P5[3]
15
I/O
M
P5[1]
16
I/O
M
P1[7]
I2C Serial Clock (SCL).
17
I/O
M
P1[5]
I2C Serial Data (SDA).
18
I/O
M
P1[3]
19
I/O
M
P1[1]
I2C Serial Clock (SCL) ISSP SCLK
[1]
.
20
Power
Vss
Ground connection.
21
USB
D+
22
USB
D-
23
Power
Vdd
Supply voltage.
24
I/O
P7[7]
25
I/O
P7[6]
26
I/O
P7[5]
27
I/O
P7[4]
28
I/O
P7[3]
29
I/O
P7[2]
Pin 
No.
Type
Name
Description
30
I/O
P7[1]
Digital
Analog
31
I/O
P7[0]
50
I/O
M
P4[6]
32
I/O
M
P1[0]
I2C Serial Data (SDA), ISSP SDATA
.
51
I/O
I,M
P2[0]
Direct switched capacitor block input.
33
I/O
M
P1[2]
52
I/O
I,M
P2[2]
Direct switched capacitor block input.
34
I/O
M
P1[4]
Optional External Clock Input (EXTCLK). 53
I/O
M
P2[4]
External Analog Ground (AGND) input.
35
I/O
M
P1[6]
54
I/O
M
P2[6]
External Voltage Reference (VREF) input.
36
I/O
M
P5[0]
55
I/O
I,M
P0[0]
Analog column mux input.
37
I/O
M
P5[2]
56
I/O
I,M
P0[2]
Analog column mux input and column output.
38
I/O
M
P5[4]
57
I/O
I,M
P0[4]
Analog column mux input and column output.
39
I/O
M
P5[6]
58
I/O
I,M
P0[6]
Analog column mux input.
40
I/O
M
P3[0]
59
Power
Vdd
Supply voltage.
41
I/O
M
P3[2]
60
Power
Vss
Ground connection.
42
I/O
M
P3[4]
61
I/O
I,M
P0[7]
Analog column mux input, integration input #1
43
I/O
M
P3[6]
62
I/O
I/O,M
P0[5]
Analog column mux input and column output, integration 
input #2.
44
NC
No connection.
63
I/O
I/O,M
P0[3]
Analog column mux input and column output.
45
NC
No connection.
64
I/O
I,M
P0[1]
Analog column mux input.
46
Input
XRES
Active high pin reset with internal pull 
down.
65
I/O
M
P2[7]
47
I/O
M
P4[0]
66
I/O
M
P2[5]
48
I/O
M
P4[2]
67
I/O
I,M
P2[3]
Direct switched capacitor block input.
49
I/O
M
P4[4]
68
I/O
I,M
P2[1]
Direct switched capacitor block input.
 
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
P2
[6
], 
M
, Ex
t.
 V
R
E
F
P
2[4]
, M, E
xt. AG
ND
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
NC
NC
Vss
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
M
, P1[3]
P7
[5
]
I2
C
 SDA,
 M, P1
[0
]
I2
C
 SC
L, M
, P1[1
]
Vs
s
D +
D -
Vd
d
P7
[6
]
P7
[4
]
P7
[3
]
P7
[2
]
P7
[1
]
P7
[0
]
M
, P1[2]
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
NC
NC
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
P
2
[1
], M, AI
P
2
[3
], M, AI
P2
[5
], M
P2
[7
], M
P
0
[1
], M, AI
P0
[3]
, M,
 AI
O
P0
[5]
, M,
 AI
O
P
0
[7
], M, AI
Vss
Vd
d
P
0
[6
], M, AI
P
0
[4
], M, AI
P
0
[2
], M, AI
P
0
[0
], M, AI
P
2
[2
], M, AI
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
QFN
(Top View)
M
, P1[4]
EX
TC
LK
,
P7
[7
]