Cypress CY7C0832BV Manual De Usuario
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Document #: 38-06059 Rev. *S
Page 10 of 28
IEEE 1149.1 Serial Boundary Scan (JTAG)
The FLEx18 family devices incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 compliant TAPs. The TAP operates
using JEDEC-standard 3.3V I/O logic levels. It is composed of
three input connections and one output connection required by
the test logic defined by the standard.
boundary scan test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 compliant TAPs. The TAP operates
using JEDEC-standard 3.3V I/O logic levels. It is composed of
three input connections and one output connection required by
the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (V
DD
) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the device is operating. An
MRST must be performed on the devices after power up.
devices, and may be performed while the device is operating. An
MRST must be performed on the devices after power up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outputs a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester should be configured to never enter the PAUSE-DR state.
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outputs a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester should be configured to never enter the PAUSE-DR state.
Boundary Scan Hierarchy for 9-Mbit Device
Internally, the CY7C0833AV have two DIEs. Each DIE contain all
the circuitry required to support boundary scan testing. The
circuitry includes the TAP, TAP controller, instruction register,
and data registers. The circuity and operation of the DIE
boundary scan are described in detail below. The scan chain of
each DIE are connected serially to form the scan chain of the
CY7C0833AV as shown in
the circuitry required to support boundary scan testing. The
circuitry includes the TAP, TAP controller, instruction register,
and data registers. The circuity and operation of the DIE
boundary scan are described in detail below. The scan chain of
each DIE are connected serially to form the scan chain of the
CY7C0833AV as shown in
on page 11. TMS and TCK
are connected in parallel to each DIE to drive all TAP controllers
in unison. In many cases, each DIE is supplied with the same
instruction. In other cases, it might be useful to supply different
instructions to each DIE. One example would be testing the
device ID of one DIE while bypassing the others.
in unison. In many cases, each DIE is supplied with the same
instruction. In other cases, it might be useful to supply different
instructions to each DIE. One example would be testing the
device ID of one DIE while bypassing the others.
Each pin of FLEx18 family is typically connected to multiple DIEs.
For connectivity testing with the EXTEST instruction, it is
desirable to check the internal connections between DIEs and
the external connections to the package. This is accomplished
by merging the netlist of the devices with the netlist of the user’s
circuit board. To facilitate boundary scan testing of the devices,
Cypress provides the BSDL file for each DIE, the internal netlist
of the device, and a description of the device scan chain. The
user can use these materials to easily integrate the devices into
the board’s boundary scan environment. Further information is
found in the Cypress application note
For connectivity testing with the EXTEST instruction, it is
desirable to check the internal connections between DIEs and
the external connections to the package. This is accomplished
by merging the netlist of the devices with the netlist of the user’s
circuit board. To facilitate boundary scan testing of the devices,
Cypress provides the BSDL file for each DIE, the internal netlist
of the device, and a description of the device scan chain. The
user can use these materials to easily integrate the devices into
the board’s boundary scan environment. Further information is
found in the Cypress application note
Using JTAG Boundary
Scan For System in a Package (SIP) Dual-Port SRAMs
.
Figure 4. Programmable Counter-Mask Register Operation
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
16
2
15
2
6
2
1
2
5
2
2
2
4
2
3
2
0
H
H
L
H
1
1
0s
1
0
1
0
1
0
1
0
0
Xs
1
X
0
X
0
X
0
1
1
Xs
1
X
1
X
1
X
1
0
0
Xs
1
X
0
X
0
X
0
Masked Address
Unmasked Address
Mask
Register
bit-0
Register
bit-0
Address
Counter
bit-0
Counter
bit-0
CNTINT
Example:
Load
Counter-Mask
Register = 3F
Counter-Mask
Register = 3F
Load
Address
Counter = 8
Address
Counter = 8
Max
Address
Register
Address
Register
Max + 1
Address
Register
Address
Register
Notes
20. The “X” in this diagram represents the counter upper bits
21. Boundary scan is IEEE 1149.1-compatible. See
21. Boundary scan is IEEE 1149.1-compatible. See
on page 10 for deviation from strict 1149.1 compliance