SMC Networks LH79520 SoC ARM720T Manual De Usuario
ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor
As the physical ARM720T processor does not reside within an FPGA, communications between the host computer and the
ARM720T are carried out through the Hard Devices JTAG chain. This is a departure from the normal way of communicating with
FPGA-based, debug-enabled devices, such as the 'soft' processors and virtual instruments, whereby communication is carried
out through the Soft Devices JTAG chain, and in accordance with the Nexus 5001 standard.
ARM720T are carried out through the Hard Devices JTAG chain. This is a departure from the normal way of communicating with
FPGA-based, debug-enabled devices, such as the 'soft' processors and virtual instruments, whereby communication is carried
out through the Soft Devices JTAG chain, and in accordance with the Nexus 5001 standard.
For further information on the JTAG communications, refer to the article
Additional 'Soft' Devices in Your Design
If your design incorporates FPGA-based 'soft' processors and virtual instruments, in addition to the discrete ARM720T
processor, these devices will appear in the Soft Devices chain of the Devices view. The Soft Devices chain is determined when
the design has been implemented within the target FPGA device. It is not a physical chain, in the sense that you can see no
external wiring – the connections required between the Nexus-enabled devices are made internal to the FPGA itself. Figure 14
shows an example of devices presented in this chain.
processor, these devices will appear in the Soft Devices chain of the Devices view. The Soft Devices chain is determined when
the design has been implemented within the target FPGA device. It is not a physical chain, in the sense that you can see no
external wiring – the connections required between the Nexus-enabled devices are made internal to the FPGA itself. Figure 14
shows an example of devices presented in this chain.
Figure 14. Nexus-enabled processor (TSK3000A) and virtual instruments appearing in the Soft Devices chain.
Enabling the Soft Devices JTAG Chain
In order to communicate with soft devices in a design (processors and/or virtual instruments) you must enable the Soft Devices
JTAG chain within the design. This is done by placing a JTAG Port (NEXUS_JTAG_CONNECTOR) and corresponding Soft Nexus-
Chain Connector (NEXUS_JTAG_PORT) on the top schematic sheet of the design, as shown in Figure 15.
JTAG chain within the design. This is done by placing a JTAG Port (NEXUS_JTAG_CONNECTOR) and corresponding Soft Nexus-
Chain Connector (NEXUS_JTAG_PORT) on the top schematic sheet of the design, as shown in Figure 15.
If your design incorporates just the
discrete ARM720T_LH79520, with
no additional 'soft' devices, then
these Nexus JTAG devices are not
required.
discrete ARM720T_LH79520, with
no additional 'soft' devices, then
these Nexus JTAG devices are not
required.
Figure 15. Implementing the soft devices chain within the design.
These devices can be found in the FPGA NB2DSK01 Port-Plugin (FPGA NB2DSK01 Port-Plugin.IntLib) and FPGA
Generic (FPGA Generic.IntLib) integrated libraries respectively, both of which are located in the \Library\Fpga folder of
the installation.
Generic (FPGA Generic.IntLib) integrated libraries respectively, both of which are located in the \Library\Fpga folder of
the installation.
Downloading Your Design
Download of a design which incorporates a discrete processor such as the ARM720T_LH79520 is performed in two stages:
• Download of the FPGA design to the target physical FPGA device. This includes downloading the respective embedded
• Download of the FPGA design to the target physical FPGA device. This includes downloading the respective embedded
code to any 'soft' processors used within the design. Click on the FPGA device in the Hard Devices chain to access the
process flow required to facilitate this part of the download, as illustrated in the following image. The standard process flow is
followed when programming the FPGA device – Compile, Synthesize, Build and Program.
process flow required to facilitate this part of the download, as illustrated in the following image. The standard process flow is
followed when programming the FPGA device – Compile, Synthesize, Build and Program.
CR0162 (v2.0) March 10, 2008
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