Cypress CY7C1443AV33 Manual De Usuario

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Document #: 38-05357 Rev. *G
Revised May 09, 2008
Page 31 of 31
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
 
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
© Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress. 
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges. 
Use may be limited by and subject to the applicable Cypress software license agreement. 
*E
417547
See ECN
RXU
Converted from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 
North First Street” to “198 Champion Court”.
Changed I
X
 current value in MODE from –5 & 30 
μA to –30 & 5 μA respectively 
and also Changed I
X
 current value in ZZ from –30 & 5 
μA to –5 & 30 μA respec-
tively on page# 19.
Modified test condition in note# 8 from V
IH
 < V
DD 
to
 
V
IH 
< V
DD.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the 
Electrical Characteristics Table.
Replaced Package Name column with Package Diagram in the Ordering 
Information table.
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information.
*F
473650
See ECN
VKN
Added the Maximum Rating for Supply Voltage on V
DDQ
 Relative to GND.
Changed t
TH
, t
TL 
from 25 ns to 20 ns and t
TDOV
 from 5 ns to 10 ns in TAP AC 
Switching Characteristics table.
Updated the Ordering Information table.
*G
2447027
See ECN
VKN/AESA Corrected typo in the Ordering Information table
Corrected typo in the CY7C1447AV33 ‘s Logic Block diagram
Updated the x72 block diagram 
Document Title: CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
Document Number: 38-05357
REV.
ECN NO.
Issue Date
Orig. of 
Change
Description of Change