Cypress CY7C0833AV Manual De Usuario
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Document #: 38-06059 Rev. *S
Page 5 of 28
Pin Definitions
Left Port
Right Port
Description
A
0L
–A
18L
A
0R
–A
18R
Address Inputs.
ADS
L
[8]
ADS
R
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for
the part using the externally supplied address on the address pins and for loading this address
into the burst address counter.
the part using the externally supplied address on the address pins and for loading this address
into the burst address counter.
CE0
L
CE0
R
Active LOW Chip Enable Input.
CE1
L
CE1
R
Active HIGH Chip Enable Input.
CLK
L
CLK
R
Clock Signal. Maximum clock input rate is f
MAX
.
CNTEN
L
CNTEN
R
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are
asserted LOW.
respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are
asserted LOW.
CNTRST
L
[7]
CNTRST
R
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the
burst address counter of its respective port. CNTRST is not disabled by asserting ADS or
CNTEN.
burst address counter of its respective port. CNTRST is not disabled by asserting ADS or
CNTEN.
CNT/MSK
L
CNT/MSK
R
Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to
the mask register. When tied HIGH, the mask register is not accessible and the address counter
operations are enabled based on the status of the counter control signals.
the mask register. When tied HIGH, the mask register is not accessible and the address counter
operations are enabled based on the status of the counter control signals.
DQ
0L
–DQ
17L
DQ
0R
–DQ
17R
Data Bus Input/Output.
OE
L
OE
R
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data
pins during Read operations.
pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations are used for message passing. INT
upper two memory locations are used for message passing. INT
L
is asserted LOW when the
right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is
deasserted HIGH when it reads the contents of its mailbox.
deasserted HIGH when it reads the contents of its mailbox.
CNTINT
L
CNTINT
R
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter
is incremented to all ‘1s.’
is incremented to all ‘1s.’
R/W
L
R/W
R
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port
memory array.
memory array.
B
0L
–B
1L
B
0R
–B
1R
Byte Select Inputs. Asserting these signals enables Read and Write operations to the corre-
sponding bytes of the memory array.
sponding bytes of the memory array.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST LOW performs all of the reset functions as described in the text. A MRST operation is
required at power up.
MRST LOW performs all of the reset functions as described in the text. A MRST operation is
required at power up.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
machine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.
TCK
JTAG Test Clock Input.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
three-stated except when captured data is shifted out of the JTAG TAP.
V
SS
Ground Inputs.
V
DD
Power Inputs.
Byte Select Operation
Control Pin
Effect
B
0
DQ
0–8
Byte Control
B
1
DQ
9–17
Byte Control