Cypress CY7C2563KV18 Manual De Usuario
PRELIMINARY
CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
CY7C2563KV18, CY7C2565KV18
Document Number: 001-15887 Rev. *E
Page 24 of 29
Switching Characteristics
Over the Operating Range
Cypress
Parameter
Consortium
Parameter
Description
550 MHz
500 MHz
450 MHz
400 MHz
Unit
Min Max Min Max Min Max Min Max
t
POWER
V
DD
(Typical) to the First Access
1
1
1
1
ms
t
CYC
t
KHKH
K Clock Cycle Time
1.81 8.4
2.0
8.4
2.2
8.4
2.5
8.4
ns
t
KH
t
KHKL
Input Clock (K/K) HIGH
0.4
–
0.4
–
0.4
–
0.4
–
ns
t
KL
t
KLKH
Input Clock (K/K) LOW
0.4
–
0.4
–
0.4
–
0.4
–
ns
t
KHKH
t
KHKH
K Clock Rise to K Clock Rise
(rising edge to rising edge)
0.77
–
0.85
–
0.94
–
1.06
–
ns
Setup Times
t
t
SA
t
AVKH
Address Setup to K Clock Rise
0.23
–
0.25
–
0.275
–
0.4
–
ns
t
SC
t
IVKH
Control Setup to K Clock Rise (RPS, WPS)
0.23
–
0.25
–
0.275
–
0.4
–
ns
t
SCDDR
t
IVKH
Double Data Rate Control Setup to Clock (K/K)
Rise (BWS
0
, BWS
1
,
BWS
2
, BWS
3
)
0.18
–
0.20
–
0.22
–
0.28
–
ns
t
SD
t
DVKH
D
[X:0]
Setup to Clock (K/K) Rise
0.18
–
0.20
–
0.22
–
0.28
–
ns
Hold Times
t
t
HA
t
KHAX
Address Hold after K Clock Rise
0.23
–
0.25
–
0.275
–
0.4
–
ns
t
HC
t
KHIX
Control Hold after K Clock Rise (RPS, WPS)
0.23
–
0.25
–
0.275
–
0.4
–
ns
t
HCDDR
t
KHIX
Double Data Rate Control Hold after Clock (K/K)
Rise (BWS
0
, BWS
1
, BWS
2
, BWS
3
)
0.18
–
0.20
–
0.28
–
0.28
–
ns
t
HD
t
KHDX
D
[X:0]
Hold after Clock (K/K) Rise
0.18
–
0.20
–
0.28
–
0.28
–
ns
Output Times
t
t
CO
t
CHQV
K/K Clock Rise to Data Valid
–
0.29
–
0.33
–
0.37
–
0.45
ns
t
DOH
t
CHQX
Data Output Hold after Output K/K Clock Rise
(Active to Active)
–0.29
–
–0.33
–
–0.37
–
–0.45
–
ns
t
CCQO
t
CHCQV
K/K Clock Rise to Echo Clock Valid
–
0.29
–
0.33
–
0.37
–
0.45
ns
t
CQOH
t
CHCQX
Echo Clock Hold after K/K Clock Rise
–0.29
–
–0.33
–
–0.37
–
–0.45
–
ns
t
CQD
t
CQHQV
Echo Clock High to Data Valid
0.15
0.15
0.15
0.20
ns
t
CQDOH
t
CQHQX
Echo Clock High to Data Invalid
–0.15
–
–0.15
–
–0.15
–
–0.20
–
ns
t
CQH
t
CQHCQL
Output Clock (CQ/CQ) HIGH
0.655
–
0.75
–
0.85
–
1.0
–
ns
t
CQHCQH
t
CQHCQH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge)
(rising edge to rising edge)
0.655
–
0.75
–
0.85
–
1.0
–
ns
t
CHZ
t
CHQZ
Clock (K/K) Rise to High-Z
(Active to High-Z)
–
0.29
–
0.33
–
0.37
–
0.45
ns
t
CLZ
t
CHQX1
Clock (K/K) Rise to Low-Z
–0.29
–
–0.33
–
–0.37
–
–0.45
–
ns
t
QVLD
t
CQHQVLD
Echo Clock High to QVLD Valid
–0.15 0.15 –0.15 0.15 –0.15 0.15 –0.20 0.20
ns
PLL Timing
t
t
KC Var
t
KC Var
Clock Phase Jitter
–
0.15
–
0.15
–
0.15
–
0.20
ns
t
KC lock
t
KC lock
PLL Lock Time (K)
20
–
20
–
20
–
20
–
μs
t
KC Reset
t
KC Reset
K Static to PLL Reset
30
30
30
30
ns
Notes
25. When a part with a maximum frequency above 400 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
26. This part has a voltage regulator internally; t
POWER
is the time that the power must be supplied above V
DD
minimum initially before a read or write operation can be
initiated.
27. These parameters are extrapolated from the input timing parameters (t
CYC
/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
28. t
CHZ
, t
CLZ
. Transition is measured ± 100 mV from steady-state voltage.
29. At any given voltage and temperature t
CHZ
is less than t
CLZ
and t
CHZ
less than t
CO
.
30. t
QVLD
spec is applicable for both rising and falling edges of QVLD signal.
31. Hold to >V
IH
or <V
IL
.