Cypress CY14B101Q3 Manual De Usuario
PRELIMINARY
CY14B101Q1
CY14B101Q2
CY14B101Q3
CY14B101Q2
CY14B101Q3
Document #: 001-50091 Rev. *A
Page 11 of 22
nvSRAM Special Instructions
CY14B101Q1/CY14B101Q2/CY14B101Q3 provides four
special instructions which enables access to four nvSRAM
specific functions: STORE, RECALL, ASDISB, and ASENB.
Software STORE
When a STORE instruction is executed, nvSRAM performs a
Software STORE operation. The STORE operation is issued
irrespective of whether a write has taken place since last STORE
or RECALL operation.
To issue this instruction, the device must be write enabled (WEN
bit = ‘1’). The instruction is performed by transmitting the STORE
opcode on the SI pin following the falling edge of CS. The WEN
Figure 12. Burst Mode Read Instruction Timing
Figure 13. Write Instruction Timing
Figure 14. Burst Mode Write Instruction Timing
CS
SCK
SO
LSB
SI
Op-Code
17-bit Address
MSB
LSB
~ ~
~ ~
~ ~
0 1
2
3
4 5 6
7
0
7
6
5
4
3
2
1
20 21 22 23 0
1
2
3 4 5
6
7
0
1
2
3
4 5
6
7
~ ~
0 7
0
0
0
0
0
0
1 1
0
0
0 0
0 0
0 A16
A3 A2 A1 A0
D0
D1
D2
D3
D4
D5
D6
D7
Data Byte 1
Data Byte N
MSB
LSB
MSB
D0
D1
D2
D3
D4
D5
D6
D7
D0
D7
~ ~
CS
SCK
SO
0
1
2
3
4
5 6 7
0
7
6
5
4
3
2
1
20 21 22 23 0
1
2
3
4
5
6
7
MSB
LSB
Data
D0
D1
D2
D3
D4
D5
D6
D7
SI
~ ~
Op-Code
0
0
0
0
0
0
1
0
0
0
0 0
0
0
0
A16
A3
A1
A2
A0
17-bit Address
MSB
LSB
HI-Z
~ ~
CS
SCK
SO
MSB
LSB
SI
Op-Code
17-bit Address
MSB
LSB
~ ~
~ ~
0 1
2
3
4 5
6
7 0
7
6
5
4
3
2
1
20 21 22 23 0 1
2
3
4 5
6
7
0 1
2
3
4 5
6
7
~ ~
0
7
0
0 0
0 0
0
1
0
0
0
0
0
0
0 0 A16 A3 A2 A1 A0
HI-Z
Data Byte 1
Data Byte N
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D7
Table 8. nvSRAM Special Instructions
Function Name
Opcode
Operation
STORE
0011 1100
Software STORE
RECALL
0110 0000
Software RECALL
ASENB
0101 1001
AutoStore Enable
ASDISB
0001 1001
AutoStore Disable