Cypress CY7C0430BV Manual De Usuario

Document #: 38-06027 Rev. *B

Page 3 of 37

counter is loaded with an external address when the port’s

Counter Load pin (CNTLD) is asserted LOW. When the port’s

Counter Increment pin (CNTINC) is asserted, the address

counter will increment on each subsequent LOW-to- HIGH

transition of that port’s clock signal. This will read/write one

word from/into each successive address location until

CNTINC is deasserted. The counter can address the entire

switch array and will loop back to the start. Counter Reset

(CNTRST) is used to reset the burst counter. A counter-mask

register is used to control the counter wrap. The counter and

mask register operations are described in more details in the

following sections.
The counter or mask register values can be read back on the

bidirectional address lines by activating MKRD or CNTRD,

respectively.
The new features included for the QuadPort DSE family

include: readback of burst-counter internal address value on

address lines, counter-mask registers to control the counter

wrap-around, readback of mask register value on address

lines, interrupt flags for message passing, BIST, JTAG for

boundary scan, and asynchronous Master Reset.

2. Port 1 Control Logic Block is detailed on page 4.
3. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.

Port-1 
Control
Logic

Port 1
Counter/
Mask Reg/
Address
Decode

Port 1
I/O

18

64K × 18
QuadPort DSE 
Array

[2]

Port 2 Logic Blocks

[3]

Port 4 Logic Blocks

[3]

Port 3 Logic Blocks

[3]

CNTLD

P1

CNTINC

P1

CNTRST

P1

MKLD

P1

CNTINT

P1

MKRD

P1

CNTRD

P1

INT

P1

CE

1P1

CE

0P1

R/W

P1

OE

P1

UB

P1

LB

P1

I/O

0P1

- I/O

17P1

A

0P1

–A

15P1

16

TMS

TCK

TDI

TDO

BIST

MRST

Reset

Logic

JTAG

Controller

CLK

P1

CLK

P1

CLKBIST

Port 1

Port 2

Port 3

Port 4