Cypress CY7C1514JV18 Manual De Usuario

Document #: 001-14435 Rev. *C

Page 21 of 26

Over the Operating Range 

V

IH

Input HIGH Voltage

V

REF

 + 0.2

–

–

V

V

IL 

Input LOW Voltage

–

–

V

REF

 – 0.2

V

Tested initially and after any design or process change that may affect these parameters.

C

IN

 Input 

Capacitance

T

A

 = 25

°C, f = 1 MHz, V

DD

 = 1.8V, V

DDQ 

= 1.5V

5.5

pF

C

CLK

Clock Input Capacitance

8.5

pF

C

O

Output Capacitance

6

pF

Tested initially and after any design or process change that may affect these parameters.

Θ

JA

Thermal Resistance
(Junction to Ambient)

Test conditions follow standard test methods and 
procedures for measuring thermal impedance, in 
accordance with EIA/JESD51.

16.2

°C/W

Θ

JC

Thermal Resistance
(Junction to Case)

2.3

°C/W

1.25V

0.25V

R = 50

Ω

5 pF

INCLUDING

JIG AND

SCOPE

ALL INPUT PULSES 

DEVICE

R

L

= 50

Ω

Z

0

= 50

Ω

V

REF 

= 0.75V

V

REF 

= 0.75V

0.75V

UNDER 
TEST

0.75V

DEVICE
UNDER
TEST

OUTPUT

0.75V

V

REF

V

REF

OUTPUT

ZQ

ZQ

(a)

SLEW RATE= 2 V/ns

RQ =
250

Ω

(b)

RQ =
250

Ω

19. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250

Ω, V

DDQ

 = 1.5V, input 

pulse levels of 0.25V to 1.25V, and output loading of the specified I

OL

/I

OH

 and load capacitance shown in (a) of 

.