Cypress CY14B101Q2 Manual De Usuario
PRELIMINARY
CY14B101Q1
CY14B101Q2
CY14B101Q3
CY14B101Q2
CY14B101Q3
Document #: 001-50091 Rev. *A
Page 16 of 22
AutoStore or Power Up RECALL
Parameters
Description
CY‘4B101QxA
Unit
Min
Max
t
FA
Power Up RECALL Duration
20
ms
t
STORE
STORE Cycle Duration
8
ms
t
DELAY
[9]
Time Allowed to Complete SRAM Cycle
25
ns
V
SWITCH
Low Voltage Trigger Level
2.65
V
t
VCCRISE
VCC Rise Time
150
μs
V
HDIS
HSB Output Driver Disable Voltage
1.9
V
t
LZHSB
HSB To Output Active Time
5
μs
t
HHHD
HSB High Active Time
500
ns
Switching Waveforms
Figure 23. AutoStore or Power Up RECALL
tSTORE
tSTORE
tHHHD
tHHHD
tDELAY
tDELAY
VVCCRISE
Note8
Note8
Note11
tLZHSB
tLZHSB
tFA
tFA
VSWITCH
VHDIS
HSB OUT
Autostore
POWER-UP
RECALL
Read and Write
Inhibited (RWI)
POWER-UP
RECALL
POWER-UP
RECALL
Read and Write
Read and Write
BROWN
OUT
AUTOSTORE
POWER
DOWN
AUTOSTORE
Notes
7. t
FA
starts from the time V
CC
rises above V
SWITCH.
8. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware Store is not initiated
9. On a Hardware STORE, Software Store / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
9. On a Hardware STORE, Software Store / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
DELAY
.
10. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V
SWITCH.
11. HSB pin is driven high to VCC only by internal 100kOhm resistor, HSB driver is disabled.