Cypress CY7C1511KV18 Manual De Usuario

Document Number: 001-00435 Rev. *E

Page 9 of 31

The CY7C1511KV18 is used with a single clock that controls

both the input and output registers. In this mode the device

recognizes only a single pair of input clocks (K and K) that control

both the input and output registers. This operation is identical to

the operation if the device had zero skew between the K/K and

C/C clocks. All timing parameters remain the same in this mode.

To use this mode of operation, the user must tie C and C HIGH

at power on. This function is a strap option and not alterable

during device operation.

The read and write ports on the CY7C1513KV18 operate

independently of one another. As each port latches the address

inputs on different clock edges, the user can read or write to any

location, regardless of the transaction on the other port. If the

ports access the same location when a read follows a write in

successive clock cycles, the SRAM delivers the most recent

information associated with the specified address location. This

includes forwarding data from a write cycle that was initiated on

the previous K clock rise.
Read access and write access must be scheduled such that one

transaction is initiated on any clock cycle. If both ports are

selected on the same K clock rise, the arbitration depends on the

previous state of the SRAM. If both ports are deselected, the

read port takes priority. If a read was initiated on the previous

cycle, the write port takes priority (as read operations cannot be

initiated on consecutive cycles). If a write was initiated on the

previous cycle, the read port takes priority (as write operations

cannot be initiated on consecutive cycles). Therefore, asserting

both port selects active from a deselected state results in alter-

nating read or write operations being initiated, with the first

access being a read.

The CY7C1513KV18 has a port select input for each port. This

enables for easy depth expansion. Both port selects are sampled

on the rising edge of the positive input clock only (K). Each port

select input can deselect the specified port. Deselecting a port

does not affect the other port. All pending transactions (read and

write) are completed before the device is deselected. 

An external resistor, RQ, must be connected between the ZQ pin

on the SRAM and V

SS 

to allow the SRAM to adjust its output

driver impedance. The value of RQ must be 5X the value of the

intended line impedance driven by the SRAM, the allowable

range of RQ to guarantee impedance matching with a tolerance

of ±15% is between 175

Ω and 350Ω

, 

with V

DDQ

= 1.5V.  The

output impedance is adjusted every 1024 cycles upon power up

to account for drifts in supply voltage and temperature.

Echo clocks are provided on the QDR-II to simplify data capture

on high speed systems. Two echo clocks are generated by the

QDR-II. CQ is referenced with respect to C and CQ is referenced

with respect to C. These are free running clocks and are synchro-

nized to the output clock of the QDR-II. In the single clock mode,

CQ is generated with respect to K and CQ is generated with

respect to K. The timing for the echo clocks is shown in the

These chips use a PLL that is designed to function between

120 MHz and the specified maximum clock frequency. During

power up, when the DOFF is tied HIGH, the PLL is locked after

20 

μs of stable clock. The PLL can also be reset by slowing or

stopping the input clocks K and K for a minimum of 30 ns.

However, it is not necessary to reset the PLL to lock to the

desired frequency. The PLL automatically locks 20 

μs after a

stable clock is presented. The PLL may be disabled by applying

ground to the DOFF pin. When the PLL is turned off, the device

behaves in QDR-I mode (with one cycle latency and a longer

access time).