Cypress CY7C0850AV Manual De Usuario
CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Document #: 38-06070 Rev. *H
Page 2 of 32
Logic Block Diagram
A
0L
–A
17L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
True
RAM Array
18
Addr.
Read
Back
Read
Back
CNTINT
L
Mask Register
Counter/
Address
Register
Register
CNT/MSK
L
Address
Decode
Dual-Ported
Interrupt
Logic
INT
L
Reset
Logic
JTAG
TDO
TMS
TCK
TDI
MRST
DQ
9L
–DQ
17L
DQ
0L
–DQ
8L
I/O
Control
9
9
9
9
DQ
18L
–DQ
26L
DQ
27L
–DQ
35L
CE
0L
CE
1L
R/W
L
B0
L
B1
L
B2
L
B3
L
OE
L
A
0R
–A
17R
CLK
R
ADS
CNTEN
CNTRST
R
18
Addr.
Read
Back
Read
Back
CNTINT
R
Mask Register
Counter/
Address
Register
Register
CNT/MSK
R
Address
Decode
Interrupt
Logic
INT
R
DQ
9R
–DQ
17R
DQ
0R
–DQ
8R
I/O
Control
9
9
9
9
DQ
18R
–DQ
26R
DQ
27R
–DQ
35R
CE
0R
CE
1R
R/W
R
B0
R
B1
R
B2
R
B3
R
OE
R
Mirror Reg
Mirror Reg
Note
1. 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits.