Cypress CY7C0832AV Manual De Usuario
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Document #: 38-06059 Rev. *S
Page 6 of 28
Master Reset
The FLEx18 family devices undergo a complete reset by taking
its MRST input LOW. The MRST input can switch asynchro-
nously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox Interrupt
(INT) flags and the Counter Interrupt (CNTINT) flags HIGH.
MRST must be performed on the FLEx18 family devices after
power up.
its MRST input LOW. The MRST input can switch asynchro-
nously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox Interrupt
(INT) flags and the Counter Interrupt (CNTINT) flags HIGH.
MRST must be performed on the FLEx18 family devices after
power up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports.
passing and permit communications between ports.
shows the interrupt operation for both ports of CY7C0833AV.
The highest memory location, 7FFFF is the mailbox for the right
port and 7FFFE is the mailbox for the left port.
The highest memory location, 7FFFF is the mailbox for the right
port and 7FFFE is the mailbox for the left port.
shows that
to set the INT
R
flag, a Write operation by the left port to address
7FFFF asserts INT
R
LOW. At least one byte has to be active for
a Write to generate an interrupt. A valid Read of the 7FFFF
location by the right port resets INT
location by the right port resets INT
R
HIGH. At least one byte
must be active for a Read to reset the interrupt. When one port
Writes to the other port’s mailbox, the INT of the port that the
mailbox belongs to is asserted LOW. The INT is reset when the
owner (port) of the mailbox Reads the contents of the mailbox.
The interrupt flag is set in a flow-through mode (that is, it follows
the clock edge of the writing port). Also, the flag is reset in a
flow-through mode (that is, it follows the clock edge of the
reading port).
Writes to the other port’s mailbox, the INT of the port that the
mailbox belongs to is asserted LOW. The INT is reset when the
owner (port) of the mailbox Reads the contents of the mailbox.
The interrupt flag is set in a flow-through mode (that is, it follows
the clock edge of the writing port). Also, the flag is reset in a
flow-through mode (that is, it follows the clock edge of the
reading port).
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT pins should be left open.
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT pins should be left open.
Address Counter and Mask Register Operations
This section describes the features only apply to 512 Kbit,1 Mbit,
2 Mbit, and 4 Mbit devices. It does not apply to 9 Mbit device.
Each port of these devices has a programmable burst address
counter. The burst counter contains three registers: a counter
register, a mask register, and a mirror register.
2 Mbit, and 4 Mbit devices. It does not apply to 9 Mbit device.
Each port of these devices has a programmable burst address
counter. The burst counter contains three registers: a counter
register, a mask register, and a mirror register.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only by
the Mask Load and Mask Reset operations and by the MRST.
The mask register defines the counting range of the counter
register. It divides the counter register into two regions: zero or
more ‘0s’ in the most significant bits define the masked region,
one or more ‘1s’ in the least significant bits define the unmasked
region. Bit 0 may also be ‘0,’ masking the least significant counter
bit and causing the counter to increment by two instead of one.
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only by
the Mask Load and Mask Reset operations and by the MRST.
The mask register defines the counting range of the counter
register. It divides the counter register into two regions: zero or
more ‘0s’ in the most significant bits define the masked region,
one or more ‘1s’ in the least significant bits define the unmasked
region. Bit 0 may also be ‘0,’ masking the least significant counter
bit and causing the counter to increment by two instead of one.
on page 8). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and by the MRST instruc-
tions.
changed only by the Counter Load, and by the MRST instruc-
tions.
on page 7 summarizes the operation of these
registers and the required input control signals. The MRST
control signal is asynchronous. All the other control signals in
control signal is asynchronous. All the other control signals in
on page 7 (CNT/MSK, CNTRST, ADS, CNTEN) are
synchronized to the port’s CLK. All these counter and mask
operations are independent of the port’s chip enable inputs (CE0
and CE1).
operations are independent of the port’s chip enable inputs (CE0
and CE1).
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and use the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This reads and writes one word from and
to each successive address location until CNTEN s deasserted.
The counter can address the entire memory array, and loops
back to the start. Counter reset (CNTRST) is used to reset the
unmasked portion of the burst counter to I/0s. A counter-mask
register is used to control the counter wrap.
operation of the address input and use the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This reads and writes one word from and
to each successive address location until CNTEN s deasserted.
The counter can address the entire memory array, and loops
back to the start. Counter reset (CNTRST) is used to reset the
unmasked portion of the burst counter to I/0s. A counter-mask
register is used to control the counter wrap.
Table 2. Interrupt Operation Example
FUNCTION
LEFT PORT
RIGHT PORT
R/W
L
CE
L
A
0L
–A
18L
INT
L
R/W
R
CE
R
A
0R
–A
18R
INT
R
Set Right INT
R
Flag
L
L
3FFFF
X
X
X
X
L
Reset Right INT
R
Flag
X
X
X
X
H
L
3FFFF
H
Set Left INT
L
Flag
X
X
X
L
L
L
3FFFE
X
Reset Left INT
L
Flag
H
L
3FFFE
H
X
X
X
X
Set Right INT
R
Flag
L
L
3FFFF
X
X
X
X
L
Notes
12. CE is internal signal. CE = LOW if CE
0
= LOW and CE
1
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.
13. OE is “Don’t Care” for mailbox operation.
14. At least one of BE0, BE1 must be LOW.
15. A18x is a NC for CY7C0832AV/CY7C0832BV, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CY7C0831AV, therefore the Interrupt
14. At least one of BE0, BE1 must be LOW.
15. A18x is a NC for CY7C0832AV/CY7C0832BV, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CY7C0831AV, therefore the Interrupt
addresses are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CY7C0830AV, therefore the Interrupt Addresses are FFFF and FFFE;A18x, A17x, A16x and A15x
are NC for CY7C0837AV, therefore the Interrupt Addresses are 7FFF and 7FFE.
are NC for CY7C0837AV, therefore the Interrupt Addresses are 7FFF and 7FFE.
16. This section describes the CY7C0832AV/CY7C0832BV, CY7C0831AV, CY7C0830AV and CY7C0837AV having 18, 17, 16 and 15 address bits.
17. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
17. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.