Cypress CY7C1329H Manual De Usuario
CY7C1329H
Document #: 38-05673 Rev. *B
Page 16 of 16
Document History Page
Document Title: CY7C1329H 2-Mbit (64K x 32) Pipelined Sync SRAM
Document Number: 38-05673
Document Number: 38-05673
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
347357
See ECN
PCI
New Data Sheet
*A
424820
See ECN
RXU
Converted from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from V
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from V
IH
< V
DD
to
V
IH
< V
DD
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Updated the Ordering Information Table.
Replaced Package Diagram of 51-85050 from *A to *B
Information table.
Updated the Ordering Information Table.
Replaced Package Diagram of 51-85050 from *A to *B
*B
433014
See ECN
NXR
Included 3.3V I/O option
Updated the Ordering Information table.
Updated the Ordering Information table.