Cypress CY62138EV30 Manual De Usuario
2-Mbit (256K x 8) MoBL
®
Static RAM
CY62138EV30
MoBL
®
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05577 Rev. *A
Revised February 14, 2006
Features
• Very high speed: 45 ns
— Wide voltage range: 2.20V – 3.60V
• Pin-compatible with CY62138CV30
• Ultra-low standby power
— Typical standby current: 1
µA
— Maximum standby current: 7
µA
• Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in Pb-free 36-ball BGA package
Functional Description
The CY62138EV30 is a high-performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption when deselected
(CE HIGH).
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption when deselected
(CE HIGH).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
A
1
COLUMN
DECODER
ROW DEC
O
D
E
R
SE
N
SE AM
PS
Data in Drivers
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
256K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
12
CE
A
13
A
14
A
15
A
16
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
17