Cypress CY62126EV30 Manual De Usuario
MoBL
®
, CY62126EV30
Document #: 38-05486 Rev. *E
Page 5 of 13
Switching Characteristics
Over the Operating Range
Parameter
Description
45 ns (Industrial)
55 ns (Automotive)
Unit
Min
Max
Min
Max
Read Cycle
t
t
RC
Read Cycle Time
45
55
ns
t
AA
Address to Data Valid
45
55
ns
t
OHA
Data Hold from Address Change
10
10
ns
t
ACE
CE LOW to Data Valid
45
55
ns
t
DOE
OE LOW to Data Valid
22
25
ns
t
LZOE
OE LOW to Low Z
5
5
ns
t
HZOE
OE HIGH to High Z
18
20
ns
t
LZCE
CE LOW to Low Z
10
10
ns
t
HZCE
CE HIGH to High Z
18
20
ns
t
PU
CE LOW to Power Up
0
0
ns
t
PD
CE HIGH to Power Down
45
55
ns
t
DBE
BHE / BLE LOW to Data Valid
22
25
ns
t
LZBE
BHE / BLE LOW to Low Z
5
5
ns
t
HZBE
BHE / BLE HIGH to High Z
18
20
ns
Write Cycle
t
WC
Write Cycle Time
45
55
ns
t
SCE
CE LOW to Write End
35
40
ns
t
AW
Address Setup to Write End
35
40
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Setup to Write Start
0
0
ns
t
PWE
WE Pulse Width
35
40
ns
t
BW
BHE / BLE Pulse Width
35
40
ns
t
SD
Data Setup to Write End
25
25
ns
t
HD
Data Hold from Write End
0
0
ns
t
HZWE
WE LOW to High Z
18
20
ns
t
LZWE
WE HIGH to Low Z
10
10
ns
Notes
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V
CC(typ)
/2, input pulse levels of 0 to V
CC(typ)
, and output loading of the
specified I
OL
/I
OH
and 30-pF load capacitance.
11. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
for further clarification.
12. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
13. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
14. The internal write time of the memory is defined by the overlap of WE, CE
= V
IL
, BHE, BLE or both = V
IL
. All signals must be active to initiate a write and any of
these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.