Texas Instruments TMS320C6455 Manual De Usuario
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DCAB
DDR2CLKOUT
DDR2CLKOUT
DDR2CLKOUT
DCE0
DSDCKE
DSDRAS
DSDWE
DSDDQM[3:0]
DSDCAS
DBA[2:0]
DEA[13:11, 9:0]
DEA[10]
Peripheral Architecture
2.4.4
Deactivation (DCAB and DEAC)
The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or
following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and
mode set register commands (MRS and EMRS). During a DCAB command, DEA10 is driven high to
ensure the deactivation of all banks.
following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and
mode set register commands (MRS and EMRS). During a DCAB command, DEA10 is driven high to
ensure the deactivation of all banks.
shows the timing diagram for a DCAB command.
Figure 6. DCAB Command
17
SPRU970G
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December 2005
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Revised June 2011
C6455/C6454 DDR2 Memory Controller
Copyright
©
2005
–
2011, Texas Instruments Incorporated