Intel 87C196CB Manual De Usuario
Index-1
A
B
Block diagram
C
address map, 7-5
bit timing, 7-10–7-12
block diagram, 7-2
bus-off state, 7-41
error detection and management logic, 7-9
message
bit timing, 7-10–7-12
block diagram, 7-2
bus-off state, 7-41
error detection and management logic, 7-9
message
overview, 7-1–7-2
programming, 7-4–7-31
receive and transmit priorities, 7-6
registers, 7-3–7-4
signals, 7-3
programming, 7-4–7-31
receive and transmit priorities, 7-6
registers, 7-3–7-4
signals, 7-3
CAN_BTIME0 register, 7-3, 7-15
CAN_BTIME1 register, 7-3, 7-16
CAN_CON register, 7-3, 7-13, 7-29
CAN_EGMSK register, 7-3, 7-19
CAN_INT register, 7-3, 7-32
CAN_MSGxCFG register, 7-3, 7-21
CAN_MSGxCON0 register, 7-3, 7-24, 7-31, 7-34
CAN_MSGxCON1 register, 7-4, 7-26
CAN_BTIME1 register, 7-3, 7-16
CAN_CON register, 7-3, 7-13, 7-29
CAN_EGMSK register, 7-3, 7-19
CAN_INT register, 7-3, 7-32
CAN_MSGxCFG register, 7-3, 7-21
CAN_MSGxCON0 register, 7-3, 7-24, 7-31, 7-34
CAN_MSGxCON1 register, 7-4, 7-26
CAN_MSGxDATA0-7 register, 7-28
CAN_MSGxDATAx register, 7-4
CAN_MSGxID register, 7-4
CAN_MSGxID0-3 register, 7-22
CAN_MSK15 register, 7-4, 7-20
CAN_SGMSK register, 7-4, 7-18
CAN_STAT register, 7-4, 7-33
CCR1 register, 9-3
CLKOUT, and internal timing, 2-2–2-4
Clock circuitry, 2-3
Clock phases, internal, 2-4
CAN_MSGxDATAx register, 7-4
CAN_MSGxID register, 7-4
CAN_MSGxID0-3 register, 7-22
CAN_MSK15 register, 7-4, 7-20
CAN_SGMSK register, 7-4, 7-18
CAN_STAT register, 7-4, 7-33
CCR1 register, 9-3
CLKOUT, and internal timing, 2-2–2-4
Clock circuitry, 2-3
Clock phases, internal, 2-4
D
E
F
Formulas
XTAL
1
I
M
Manual contents, summary, 1-1
Memory mapping
Memory mapping
INDEX