Intel 87C196CB Manual De Usuario
![Intel](https://files.manualsbrain.com/attachments/5a71b1e7f60391972dadeef20435931cbf4621a5/common/fit/150/50/86c99b5f14aeb2708e9a9e1b5305af4ccf882c1af0155dad25413c2ed84e/brand_logo.png)
87C196CB SUPPLEMENT
7-34
.
CAN_MSG
x
CON0
(
n
= 1–15)
Address:
1E
x
0H (
x
=1–F)
Reset State:
Unchanged
Program the CAN message object
x
control 0 register (CAN_MSGxCON0) to indicate whether the
message object is ready to transmit and to control whether a successful transmission or reception
generates an interrupt. The most-significant bit-pair indicates whether an interrupt is pending.
generates an interrupt. The most-significant bit-pair indicates whether an interrupt is pending.
This register consists of four bit-pairs — the most-significant bit of each pair is in true form and the
least-significant bit is in complement form. This format allows software to set or clear any bit with a
single write operation, without affecting the remaining bits.
least-significant bit is in complement form. This format allows software to set or clear any bit with a
single write operation, without affecting the remaining bits.
7
0
MSGVAL
MSGVAL
TXIE
TXIE
RXIE
RXIE
INT_PND
INT_PND
Bit
Number
Bit
Mnemonic
Function
7:6
MSGVAL
Message Object Valid
5:4
TXIE
Transmit Interrupt Enable
3:2
RXIE
Receive Interrupt Enable
1:0
INT_PND
Interrupt Pending
This bit-pair indicates that the CAN peripheral has initiated a transmit (TX)
or receive (RX) interrupt. Software must clear this bit when it services the
interrupt.
or receive (RX) interrupt. Software must clear this bit when it services the
interrupt.
01 = no interrupt
10 = an interrupt was generated
10 = an interrupt was generated
Figure 7-21. CAN Message Object
x Control 0 (CAN_MSGxCON0) Register