Renesas 16-bit single-chip microcomputer Manual De Usuario

Rev.1.02    Jul 01, 2005    page 220 of 314
REJ09B0126-0102

M16C/6N Group (M16C/6NL, M16C/6NN)

18. CAN Module

This document is under development and its contents are subject to change.

Figure 18.21 shows the behavior of the module when receiving two consecutive CAN messages, that fit

into the slot of the shown C0MCTLj register (j = 0 to 15) and  leads to losing/overwriting of the first

message.

CANbus

RecReq bit

InvalData bit

CAN0 Successful

Reception Interrupt

RecState bit

RecSucc bit

MBOX bit

NewData bit

SOF

ACK

EOF

EOF

IFS

IFS

SOF

Receive slot No.

MsgLost bit

C0MCTLj register

C0STR register

(1)

(2)

(2)

(3)

(4)

(5)

(5)

(5)

j = 0 to 15

ACK

(1) On monitoring a SOF on the CAN bus the RecState bit in the C0STR register becomes “1” (CAN

module is receiver) immediately, given the module has no transmission pending.

(2) After successful reception of the message, the NewData bit in the C0MCTLj register of the receiving

slot becomes “1” (stored new data in slot). The InvalData bit in the C0MCTLj register becomes “1”

(message is being updated) at the same time and the InvalData bit becomes “0” (message is valid)

again after the complete message was transferred to the slot.

(3) When the interrupt enable bit in the C0ICR register of the receiving slot = 1 (interrupt enabled), the

CAN0 successful reception interrupt request is generated and the MBOX bit in the C0STR register is

changed. It shows the slot number where the message was stored and the RecSucc bit in the C0STR

register is active.

(4) Read the message out of the slot after setting the New Data bit to “0” (the content of the slot is read or

still under processing by the CPU) by a program.

(5) If the NewData bit is set to “0” by a program or the next CAN message is received successfully before

the receive request for the slot is canceled, the MsgLost bit in the C0MCTLj register is set to “1”

(message has been overwritten). The new received message is transferred to the slot. Generating of

an interrupt request and change of the C0STR register are same as in 3).