Fujitsu FR81S Manual De Usuario
CHAPTER 34: CLOCK SUPERVISOR
2. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK SUPERVISOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
4
2. Configuration
This section shows the configuration of the clock supervisor.
The blocks that make up the clock supervisor are shown below.
・
Clock supervisor
・
Timeout counter
・
Control logic
・
CR oscillator
Figure 2-1 Block Diagram (detailed)
* : External reset: On assert of RSTX pin (including simultaneous assert with NMIX)
Note:
The sub clock supervisor can be used for dual clock products.
Control Logic
32-bit peripheral
MSVE
RCE
5
6
SM
MM
SCKS
7
4
3
2
1
0
SSVE
-
-
CSVCR
RC-Oscillator
Timeout Counter
RC_CLK
RST level reset
* External reset
Power-on reset
Oscillation stable
state signal
RC_CLK
Sub clock missing
detected
Main
Oscillation
MAIN Clock
Supervisor
Main clock
stable state
signal
MUX
Main clock
Sub Clock
Supervisor
Sub
Oscillation
MUX
Sub clock
Sub clock stable
state signal
RC_CLK
NO_MCLK
NO_SCLK
1/2
Su
b
cl
ock
su
pe
rvi
so
r
oper
at
ion
enabl
e
M
ai
n
cl
ock
su
pe
rvi
so
r
oper
at
ion
enabl
e
Main clock missing
detected
Sync
Stage
Sync
Stage
MB91520 Series
MN705-00010-1v0-E
1177