Fujitsu FR81S Manual De Usuario
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
21
[I
2
C]
⋅
This bit enables or disables the output of transmission interrupt request to the CPU.
⋅
When the TIE bit and the SSR:TDRE bit are set to "1", a transmission interrupt request will be output.
Note:
Set this bit to “0” when transmitting data with the use of INT bit of I
2
C bus control register (IBCR) while
DMA mode is disabled (SSR:DMA=0).
[bit1] SCKE (Serial ClocK Enable): Serial clock output enable bit
[CSIO]
This bit controls the I/O ports of a serial clock.
When this bit is set to "0": The SCK pin functions as a general-purpose I/O port or serial clock input pin.
When this bit is set to "1": It becomes a serial clock output pin allowing clock output while transmitting.
Notes:
⋅
When you use a SCK pin as a serial clock input (SCKE=0), set a general purpose input/output port to an
input port.
⋅
After SCINV bit is set, set serial clock output enable (SCKE=1).
⋅
When you use a SCK pin as a serial clock output, set the SCK pin as a peripheral output pin (set with
EPFR). See “CHAPTER: I/O PORTS” for how to make setups.
[UART][LIN-UART][I
2
C]
This bit is reserved bit. Always set this bit to "0".
[bit0] SOE (Serial Output Enable): Serial data output enable bit
[UART][CSIO][LIN-UART]
This bit enables/disables output of serial data.
When this bit is set to "0": The SOUT pin functions as a general-purpose I/O port.
When this bit is set to "1": The SOUT pin functions as a serial data output pin (SOUT).
Note:
Set a SOT pin as a peripheral output pin (set with EPFR). See “CHAPTER: I/O PORTS” for how to make
setups.
[I
2
C]
This bit is reserved bit. Always set this bit to "0".
MB91520 Series
MN705-00010-1v0-E
1334