Fujitsu FR81S Manual De Usuario
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
260
Figure 7-10 LIN ID parity error detection object
The range of detection of the LIN ID parity error is ID data and byte data of a parity. The start bit and the
stop bit are outside the LIN ID parity error detection ranges. When "L" level is detected on the stop bit, the
error is the framing error (SSR:FRE=1).
In the LIN assist mode (LAMCR:LAMEN=1), when the LIN ID parity error occurs during the transmission
of an automatic header, the automatic header transmission completion flag is set (LAMSR:LAHC=1).
When the LIN ID parity error occurs while receiving an automatic header, the automatic header (reception)
completion flag is set (LAMSR:LAHC=1) as well.
When the LIN ID parity error is detected, transmission/reception of the response stops in the assist mode.
While the LIN ID parity error flag is set (LAMESR:LPTER=1), the operation enable bit of the reception
FIFO is cleared (FCR0:FE1 or FCR0:FE2=0).
Note:
Even though the framing error is detected in the ID Field, the result of ID parity arithmetic operation is
indicated. The result at this time, however, is not guaranteed.
LIN ID parity error detection interrupt and flag setting timing on master side
On master side (SCR:MS=0) set in the assist mode (LAMCR:LAMEN=1), detection of the LIN ID parity
error is performed when the ID Field is transmitted. The master does the parity arithmetic operation for the
six-bit Frame ID which is set by the transmission data register (TDR) or the LIN assist mode transmission
ID register (LAMTID). Then the ID Field automatically generated is transmitted.
When the master receives the ID Field by self-check, and if there is a difference of parity between the result
of the arithmetic operation for Frame ID and received value, the LIN ID parity error is detected and the flag
is set (LAMESR:LPTER=1).
At that time, the interrupt occurs if the interrupt is set to be enabled (LAMIER:LPTERIE=1).
LIN ID parity error detection interrupt and flag setting timing on slave side
On slave side (SCR:MS=1) set in the assist mode (LAMCR:LAMEN=1), detection of the LIN ID parity
error is performed when the ID Field is received. If the result of parity arithmetic operation for the Frame
ID value in the received ID Field is different from the received parity value, the LIN ID parity error is
detected and the flag is set (LAMESR:LPTER=1).
At that time, the reception interrupt occurs if the interrupt is set to be enabled (LAMIER:LPTERIE=1).
SIN
SOUT
MPU
(header/response transmission node)
Transceiver
Transmission data
Reception data
(self-check)
LIN ID parity error
Detect ion object
Transceiver
SIN
SOUT
MPU
(header/response reception node)
Reception data
LIN ID parityerror
Dete ction o bject
MB91520 Series
MN705-00010-1v0-E
1573