Fujitsu FR81S Manual De Usuario
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
323
8.1. Interrupts of I
2
C
Interrupts of I
2
C is shown.
The I
2
C interface can generate interrupt requests caused by the following factors:
⋅
After transmission and reception of the first byte/after data transmission and reception
⋅
Stop condition
⋅
Repeated start condition
⋅
FIFO transmission data request
⋅
FIFO reception data completion
8.1.1. List of Interrupts of I
2
C Interface
The following table indicates how I
2
C interface interrupt control bits relate to interrupt factors.
Table 8-1 I
2
C Interface Interrupt Control Bits and Interrupt Factors
Interrupt
type
Interrupt
request
flag bit
Flag
register
Interrupt factor
Interrupt
factor
enable bit
Clearing of interrupt request
flag
Status
INT
IBCR
After transmission and
reception of the first
byte
*1
IBCR:INTE
Writing "0" to the interrupt flag bit
(IBCR:INT)
After data transmission
and reception
*1
Bus error detected
Arbitration lost detected
Reserved address
detected
NACK reception
Reception FIFO full
during slave reception
Writing "0" to INT after reading the
reception data till the reception
FIFO becomes empty
SPC
IBSR
Stop condition
IBCR:CNDE
Writing "0" to SPC
RSC
Repeated start detected
Writing "0" to RSC
TINT
SACSR
Serial Timer Register
(STMR) matched Serial
Timer Comparison
Register (STMCR)
SACSR:TINT
E
Writing "0" to timer interrupt flag
bit (SACSR:TINT)
MB91520 Series
MN705-00010-1v0-E
1636