Fujitsu FR81S Manual De Usuario
CHAPTER 3: CPU
10. Memory Protection Function (MPU)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CPU
FUJITSU SEMICONDUCTOR CONFIDENTIAL
40
10.3.8.
Protection Area Base Address Register 0 to 7 :
PABR0 to PABR7
PABR0 to PABR7
The bit configuration of protection area base address register 0 to 7 is shown.
These registers set the base addresses of the protection areas for each MPU channel.
PABR0 to PABR7 : Address 0330
H
, 0338
H
, 0340
H
• • • (Access : Word)
bit31
bit30
• • •
bit10
Bit9
bit8
PABR[31:8]
Initial value
X
X
• • •
X
X
X
Attribute R/W
R/W
• • •
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PABR[7:0]
Initial value
X
X
X
X
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R0,WX R0,WX R0,WX R0,WX
[bit31 to bit0] PABR[31:0] (Protection Area Base Address Register)
These registers point to the base address of the protection area. The area from the address specified here to
the size specified by the protection area control registers (PACR0 to PACR7) is the protection area. The
address does not need to be aligned to the protection area size.
The lower 4 bits of the PABR register are fixed at 0000
B
.
MB91520 Series
MN705-00010-1v0-E
137