Fujitsu FR81S Manual De Usuario
CHAPTER 48: WAVEFORM GENERATOR
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WAVEFORM GENERATOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
25
SIGCR20: Address 12B3
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PSEL21 PSEL20 PSEL11 PSEL10 PSEL01 PSEL00 Reserved
DTTI
Initial values
0
0
0
0
0
0
0
1
Attributes
R/W
R/W
R/W
R/W
R/W
R/W
R0,W0
R/W
[bit7, bit6] PSEL21, PSEL20: PPG input channel selection bits (RTO4, RTO5)
PSEL21 PSEL20
Function
0
0
PPG0/PPG8
0
1
PPG2/PPG10
1
0
PPG4/PPG12
1
1
Setting prohibited (operation is not guaranteed)
⋅
These bits are used to select the PPG input for the RTO4 and RTO5.
⋅
These bits are also used to select the GATE output destination for PPG.
⋅
Settings of "11
B
" is prohibited.
[bit5, bit4] PSEL11, PSEL10: PPG input channel selection bits (RTO2, RTO3)
PSEL11 PSEL10
Function
0
0
PPG0/PPG8
0
1
PPG2/PPG10
1
0
PPG4/PPG11
1
1
Setting prohibited (operation is not guaranteed)
⋅
These bits are used to select the PPG input for the RTO2 and RTO3.
⋅
These bits are also used to select the GATE output destination for PPG.
⋅
Settings of "11
B
" is prohibited.
[bit3, bit2] PSEL01, PSEL00: PPG input channel selection bits (RTO0, RTO1)
PSEL01 PSEL00
Function
0
0
PPG0/PPG8
0
1
PPG2/PPG10
1
0
PPG4/PPG11
1
1
Setting prohibited (operation is not guaranteed)
⋅
These bits are used to select the PPG input for the RTO0 and RTO1.
⋅
These bits are also used to select the GATE output destination for PPG.
⋅
Settings of "11
B
" is prohibited.
[bit1] Reserved
Always write 0 to this bit.
[bit0] DTTI: Software DTTI setting bit
DTTI
Function
0
DTTI set
1
DTTI clear
⋅
Writing "0" will set the DTTI.
⋅
Writing "1" will clear the DTTI.
Note:
Since it computes the logical OR with an external input DTTI, DTTI depends on the external input level.
MB91520 Series
MN705-00010-1v0-E
2070