Fujitsu FR81S Manual De Usuario
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
29
4.20. DMA Request Clear Register 21 : ICSEL21 (Interrupt
Clear SELect register 21)
The bit configuration of DMA request clear register 21 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #60).
ICSEL21: Address 0415
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
BT_SG_SEL0[1:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] BT_SG_SEL0[1:0] (BT_SG Selection0) : Interrupt clear selection bits for Base Timer0
IRQ0, IRQ1/ SG2
BT_SG_SEL0[1:0]
Clear target
00
Base Timer0 IRQ0
01
Base Timer0 IRQ1
10
Reserved (Does not clear any)
11
Reserved (Does not clear any)
Note:
Setting BT_SG_SEL0[1:0]= "10" and "11" are prohibited. During this setting, no interrupt clear will be
selected.
MB91520 Series
MN705-00010-1v0-E
374