Fujitsu FR81S Manual De Usuario
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
33
4.24. DMA Request Clear Register 25 : ICSEL25 (Interrupt
Clear SELect register 25)
The bit configuration of DMA request clear register 25 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #48).
ICSEL25: Address 0439
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
AD_SEL[4:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit4 to bit0] AD_SEL[4:0] (AD_Selection) : Interrupt clear selection bits for ADC ch.0 to ch.31
AD_SEL[4:0]
Clear target
00000
A/D converter ch.0
00001
A/D converter ch.1
00010
A/D converter ch.2
00011
A/D converter ch.3
00100
A/D converter ch.4
00101
A/D converter ch.5
00110
A/D converter ch.6
00111
A/D converter ch.7
01000
A/D converter ch.8
01001
A/D converter ch.9
01010
A/D converter ch.10
01011
A/D converter ch.11
01100
A/D converter ch.12
01101
A/D converter ch.13
01110
A/D converter ch.14
01111
A/D converter ch.15
10000
A/D converter ch.16
10001
A/D converter ch.17
10010
A/D converter ch.18
10011
A/D converter ch.19
10100
A/D converter ch.20
10101
A/D converter ch.21
10110
A/D converter ch.22
10111
A/D converter ch.23
11000
A/D converter ch.24
11001
A/D converter ch.25
MB91520 Series
MN705-00010-1v0-E
378