Fujitsu FR81S Manual De Usuario
CHAPTER 11: I/O PORTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : I/O PORTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
45
4.8. KEY CoDe Register : KEYCDR
The bit configuration of key code register is shown.
This is the register for the register writing settings that include the error writing protection function. If
writing to this register is not executed according to the specified method, writing to the target register will
become invalid. This register is only enabled for half-word access.
KEYCDR : Address 0F44
H
(Access: Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
KEY1
KEY0
SIZE
RADR12 RADR11 RADR10 RADR9
RADR8
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
RADR7
RADR6
RADR5
RADR4
RADR3
RADR2
RADR1
RADR0
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
[bit15, bit14] KEY1, KEY0: Key code
Key code setting bits. It is necessary to write continuously to this bit according to the order “00”, “01”, “10”, and
“11”.
Note:
When the writing order becomes different, the key code setting will become invalid and it will be necessary
to reset them from the beginning.
[bit13] SIZE: Access size
The access size is set for writing to the key code target register. Write the same data to the bit when writing the
key code according to the order “00”, “01”, “10”, and “11”.
SIZE
Description
0
Set byte access
1
Set half-word access
Notes:
⋅
When different data is written while writing the key code “00”, “01”, “10”, and “11”, the key code
setting will become invalid and it will be necessary to reset it from the beginning.
⋅
Word access for the key code target register is prohibited.
MB91520 Series
MN705-00010-1v0-E
440