Fujitsu FR81S Manual De Usuario
CHAPTER 17: PPG
2. Features
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
4
2. Features
This section explains features of the PPG.
Clamp output
Normal polarity: Output clamped to "L"
Inverted polarity: Output clamped to "H"
Count clock
One of the following 4 count clocks is selected:
Outputs obtained by dividing the frequency of the peripheral clock by 1, 4, 16, and 64.
Cycle
Setting range = Duty value to 65535 (specified by a 16-bit register)
Cycle = Count clock
(PCSR register value + 1)
(Example) Count clock = 32 MHz (31.25 ns), PCSR value = 63999
Cycle = 31.25ns
Cycle = 31.25ns
(63999+1) = 2ms
* Cycle Setting (PHCSR/PLCSR) for the High/Low format at the PPG communication mode is also
similar.
similar.
Duty
Setting range = 0 to cycle value (specified by a 16-bit register)
Duty = Count clock (PDUT register value + 1)
*Duty setting (PHDUT/PLDUT) for the High/Low format at the PPG communication mode is also
similar.
similar.
Output Waveforms
PWM Waveform
Duty
Cycle
Normal
Polarity
Inverted
Polarity
L
H
H
L
L
H
H
L
L
H
H
L
Duty
Cycle
Normal
Polarity
Inverted
Polarity
L
H
H
L
L
H
L
H
H
L
L
H
Normal Wave Form
Center Aligned Wave Form
* Cycle and duty are double as compared to when selecting
normal waveform.
MB91520 Series
MN705-00010-1v0-E
545