Fujitsu FR81S Manual De Usuario
CHAPTER 1: OVERVIEW
4. Function overview
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : OVERVIEW
FUJITSU SEMICONDUCTOR CONFIDENTIAL
23
Function
Features
A/D Converter
With built-in A/D converter 2 units of resolution in 12-bit
Able to sample the analog value from up to 48 channels input port
Conversion time : 12-bit A/D Converter 1μs
External trigger activation
Can be activated by an internal timer (16-bit reload timer/compare match/PPG are
used).
Has the function of selecting the sampling time for each channel.
Built-in range comparator
Has the function of selecting the sampling time for each channel.
D/A Converter
Built-in D/A converter 2 channels of resolution in 8-bit
Multi-function serial
(4 channels)
Any of UART/CSIO/LIN-UART/I
2
C-UART functions can be selected and used.
Transmission FIFO memory 16-byte, and reception FIFO memory 16-byte provided
Reception interrupt cause (3 types)
- Reception error detection (parity, overrun, and frame error)
- Detects FIFO’s reception of data up to an amount of its threshold.
- Detects the idling period which is 8 × baud rate clock or more, when amount of the data
received is less than FIFO’s threshold.
Transmission interrupt cause (2 types)
- No transmission operation.
- Empty transmission FIFO memory (including the time of transmission)
SPI (Serial Peripheral Interface) supported
LIN protocol revision 2.1 supported
I
2
C (ch.3, ch.4) 100kbps and 400kbps supported
I
2
C (ch.5 to ch.8, ch.10, ch.11) only 100kbps supported
Interrupt controller
Detects an interrupt request.
Sets an interrupt level.
Interrupt request batch read
A generation of multiple interrupts from peripherals can be read by a series of
registers.
CAN interface
CAN Specifications Version 2.0, Part A and Part B satisfied
Up to 64 message buffers × 2channel, 128 message buffers × 1channels
Support plural messages
Flexible composition of acceptance filter :
Entire bit compare
Entire bit Mask
2 portion bit Mask
Up to 1Mbps supported.
CAN prescaler is mounted for the CAN operation clock
CAN wakeup function
CAN clock source can switch main clock/PLL clock.
U/D counter (2 channels)
8/16-bit up/counter × 2channels
Software watchdog
It counts while CPU is working.
Stops counting when the CPU is stopped.
The intervals can be selected from 16 types (PCLK × (2
9
to 2
24
) cycles).
The lower limit of the term of validity to clear can be set up to 16 ways.
Hardware watchdog
CR-based CPU operation detection counter
Used against program overrun
Period: 218ms to 655ms (usually 328ms, depending on the accuracy of the CR oscillation)
Note that as shown above, a period of the CR oscillation clock varies widely due to the
production process.
CRC generation
When data is sequentially written in the input registers, the CRC code is displayed in the
result register.
MB91520 Series
MN705-00010-1v0-E
22