Fujitsu FR81S Manual De Usuario
CHAPTER 20: RELOAD TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RELOAD TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
47
5.3.7. Capture Mode
The capture mode is shown below.
When bit15, bit14:MOD[1:0] of the TMCSR register =11, the timer will perform capture operation. When a
retrigger occurs, TMRLRB register captures the TMR value and sets bit7:EF of the TMCSR register.
retrigger occurs, TMRLRB register captures the TMR value and sets bit7:EF of the TMCSR register.
When you use TIN input as the gate input (when bit8:GATE=1 of the TMCSR register), generate a retrigger
by bit0:TRG of the TMCSR register.
by bit0:TRG of the TMCSR register.
In a mode other than trigger, a capture will not be performed at a retrigger. The EF bit interrupt will also not
be generated.
be generated.
The timer operation and the TOUT output will be the same for the single one-shot feature and the single
reload feature.
reload feature.
Note:
TOUT is not initialized in the one shot mode at retrigger.
Figure 5-18 Operation of Capture
0
Counter
value
Trigger input
Retrigger input
Underflow
Underflow
Capture TMR
to TMRLRB
UF interrupt
&
Reload (TMRLRA)
EF interrupt
&
Capture (TMRLRB)
&
Reload (TMRLRA)
TMRLRA
MB91520 Series
MN705-00010-1v0-E
774