Fujitsu FR81S Manual De Usuario
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
10
4.1.3. List of Message Interface Register
This section shows the list of message interface register.
Table 4-2 List of Message Interface Register
Address
Registers
Note
+0
+1
+2
+3
Base-addr + 10
H
IF1 command request register
(IF1CREQ)
IF1 command mask register
(IF1CMSK)
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
BUSY
Mess. No. [5:0] Reserved bits
See the
IF1CMSK.
Reset: 00
H
Reset: 01
H
Reset: 00
H
Reset: 00
H
Base-addr + 14
H
IF1 mask register 2
(IF1MSK2)
IF1 mask register 1
(IF1MSK1)
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
MXtd, MDir,
Msk[28:24]
Msk[23:16]
Msk[15:8]
Msk[7:0]
Reset: FF
H
Reset: FF
H
Reset: FF
H
Reset: FF
H
Base-addr + 18
H
IF1 arbitration register 2
(IF1ARB2)
IF1 arbitration register 1
(IF1ARB1)
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
MsgVal, Xtd,
Dir, ID[28:24]
ID[23:16]
ID[15:8]
ID[7:0]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + 1C
H
IF1 message control register
(IF1MCTR)
Reserved bits
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
See the
IF1MCTR.
See the
IF1MCTR.
-
-
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + 20
H
IF1 data A register 1
(IF1DTA1)
IF1 data A register 2
(IF1DTA2)
Byte order:
Big Endian
bit[7:0]
bit[15:8]
bit[7:0]
bit[15:8]
Data[0]
Data[1]
Data[2]
Data[3]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
MB91520 Series
MN705-00010-1v0-E
1703