Gateway ALR 9200 Manual De Usuario
178 Maintaining and Troubleshooting the Gateway ALR 9200 Server
System I/O Addresses
Table 37 shows the location in I/O space of all directly I/O-accessible
registers.
registers.
Table 37: System I/O Addresses
Address
Resource
Device
Notes
0000h - 000Fh
DMA Controller 1
PIIX4E
0010h - 001Fh
DMA Controller 1
PIIX4E
Aliased from 0000h - 000Fh
0020h - 0021h
Interrupt Controller 1
PIIX4E
0022h - 0023h
0024h - 0025h
Interrupt Controller 1
PIIX4E
Aliased from 0020h - 0021h
0026h - 0027h
0028h - 0029h
Interrupt Controller 1
PIIX4E
Aliased from 0020h - 0021h
002Ah - 002Bh
002Ch - 002Dh
Interrupt Controller 1
PIIX4E
Aliased from 0020h - 0021h
002Eh - 002Fh
Super I/O Index and Data
Ports
Ports
0030h - 0031h
Interrupt Controller 1
PIIX4E
Aliased from 0020h - 0021h
0032h - 0033h
0034h - 0035h
Interrupt Controller 1
PIIX4E
Aliased from 0020h - 0021h
0036h - 0037h
0038h - 0039h
Interrupt Controller 1
PIIX4E
Aliased from 0020h - 0021h
003Ah - 003Bh
003Ch - 003Dh
Interrupt Controller 1
PIIX4E
Aliased from 0020h - 0021h
003Eh - 003Fh
0040h - 0043h
Programmable Timers
PIIX4E
0044h - 004Fh
0050h - 0053h
Programmable Timers
PIIX4E
Aliased from 0040h - 0043h
0054h - 005Fh
0060h, 0064h
Keyboard Controller
Keyboard chip select from
87307
87307
0061h
NMI Status & Control
Register
Register
PIIX4E
0063h
NMI Status & Control
Register
Register
PIIX4E
Aliased
0065h
NMI Status & Control
Register
Register
PIIX4E
Aliased
0067h
NMI Status & Control
Register
Register
PIIX4E
Aliased
3424.boo Page 178 Wednesday, September 2, 1998 9:23 AM