AMD 10 Manual De Usuario
18
Power Management
Chapter 4
AMD Athlon™ XP Processor Model 10 Data Sheet
26237C—May 2003
Preliminary Information
4.3
Clock Control
The processor implements a Clock Control (CLK_Ctl) MSR
(address C001_001Bh) that determines the internal clock
divisor when the AMD Athlon system bus is disconnected.
(address C001_001Bh) that determines the internal clock
divisor when the AMD Athlon system bus is disconnected.
Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,
Software, and Debug Developers Guide, order# 21656, for more
details on the CLK_Ctl register.
Software, and Debug Developers Guide, order# 21656, for more
details on the CLK_Ctl register.