Motorola MVME5100 Manual De Usuario
2-92
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
The PPC Slave Attributes Register 3 (XSATT3) contains attribute
information associated with the mapping of PPC memory space to PCI I/O
space. The bits within the XSATT3 register are defined as follows:
information associated with the mapping of PPC memory space to PCI I/O
space. The bits within the XSATT3 register are defined as follows:
REN
Read Enable. If set, the corresponding PPC Slave is
enabled for read transactions.
enabled for read transactions.
WEN
Write Enable. If set, the corresponding PPC Slave is
enabled for write transactions.
enabled for write transactions.
WPEN
Write Post Enable. If set, write posting is enabled for the
corresponding PPC Slave.
corresponding PPC Slave.
IOM
PCI I/O Mode. If set, the corresponding PPC Slave
generates PCI I/O cycles using spread addressing as
defined in the section on
generates PCI I/O cycles using spread addressing as
defined in the section on
. When
clear, the corresponding PPC Slave generates PCI I/O
cycles using contiguous addressing.
cycles using contiguous addressing.
WDTxCNTL Registers
The Watchdog Timer Control Registers (WDT1CNTL and
WDT2CNTL) are used to provide control information to the watchdog
timer functions within the PHB. The fields within WDTxCNTL registers
are defined as follows:
WDT2CNTL) are used to provide control information to the watchdog
timer functions within the PHB. The fields within WDTxCNTL registers
are defined as follows:
Address
WDT1CNTL - $FEFF0060
WDT2CNTL - $FEFF0068
WDT2CNTL - $FEFF0068
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
WDTxCNTL
KEY
ENAB
AR
M
RES
RELOAD
Operation
W
R/
W
R
R
R/W
R/W
Reset
$00
1
0
00
$7 or $8
$FF