Motorola MVME5100 Manual De Usuario
2-110
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
MPIC Registers
The following conventions are used in the Hawk register charts:
❏
R - Read Only field.
❏
R/W - Read/Write field.
❏
S - Writing a ONE to this field sets this field.
❏
C - Writing a ONE to this field clears this field.
MPIC Registers
The MPIC register map is shown in
. The "Off" field is the
address offset from the base address of the MPIC registers in the PPC-IO
or PPC-Memory space. Note that this map does not depict linear
addressing. The PCI-SLAVE of the PHB has two decoders for generating
the MPIC select. These decoders will generate a select and acknowledge
all accesses which are in a reserved 256K byte range. If the index into that
256K block does not decode a valid MPIC register address, the logic will
return $00000000.
or PPC-Memory space. Note that this map does not depict linear
addressing. The PCI-SLAVE of the PHB has two decoders for generating
the MPIC select. These decoders will generate a select and acknowledge
all accesses which are in a reserved 256K byte range. If the index into that
256K block does not decode a valid MPIC register address, the logic will
return $00000000.
The registers are 8, 16, or 32 bits accessible.
Table 2-19. MPIC Register Map
3
1
1
3
0
0
2
9
9
2
8
8
2
7
7
2
6
6
2
5
5
2
4
4
2
3
3
2
2
2
2
1
1
2
0
0
1
9
9
1
8
8
1
7
7
1
6
6
1
5
5
1
4
4
1
3
3
1
2
2
1
1
1
1
0 9 8 7 6 5 4 3 2 1 0
0 9 8 7 6 5 4 3 2 1 0
Off
FEATURE REPORTING REGISTER 0
$01000
GLOBAL CONFIGURATION REGISTER 0
$01020
MPIC VENDOR IDENTIFICATION REGISTER
$01080
PROCESSOR INIT REGISTER
$01090
IPI0 VECTOR-PRIORITY REGISTER
$010a0
IPI1 VECTOR-PRIORITY REGISTER
$010b0
IPI2 VECTOR-PRIORITY REGISTER
$010c0
IPI3 VECTOR-PRIORITY REGISTER
$010d0