Motorola MVME5100 Manual De Usuario
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PCI Local Bus
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1-27
1
TBEN Bit Register
The MVME5100 implementation of this register is fully compliant with
the PowerPlus II Programming Specification, with exceptions to Bit RD6,
as indicated in the following table:
the PowerPlus II Programming Specification, with exceptions to Bit RD6,
as indicated in the following table:
The TBEN Bit register provides the means to control the Processor
Timebase Enable input.
Timebase Enable input.
TBEN0
Processor 0 Time Base Enable. When this bit is cleared, the TBEN
pin of Processor 0 will be driven low. When this bit is set, the
TBEN pin is driven high.
TBEN pin is driven high.
TBEN1
This bit is not used.
Table 1-14. TBEN Bit Register
REG
TBEN Bit Register - Offset 80C0h
BIT
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
FIELD
TB
EN1
(NOT USED)
TB
EN0
OPER
R
R
R
R
R
R
R/W
R/W
RESET
X
X
X
X
X
X
1
1
REQUIRED
OR
OPTIONAL
X
X
X
X
X
X
O
R