Cisco Systems NPE-225 Manual De Usuario

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4-3
Network Processing Engine and Network Services Engine Installation and Configuration
OL-4448-12
Chapter 4      NSE-1 Overview
NSE-1 Description and Overview
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System controller
The system controller provides hardware logic to interconnect the processor, DRAM, and the 
PCI-based system backplane bus. The NSE-1 has one system controller that provides processor 
access to the two midplane and single I/O controller PCI buses. The system controller also allows 
port adapters—on either of the two midplane PCI buses—access to SDRAM.
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Upgradable memory modules
The NSE-1 uses SDRAM for providing code, data, and packet storage.
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Cache memory
The NSE-1 has three levels of cache: primary and secondary cache that are internal to the 
microprocessor with secondary unified cache for data and instruction, and tertiary, 2-MB external 
cache. 
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Two environmental sensors for monitoring the cooling air as it leaves the chassis
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Boot ROM for storing sufficient code for booting the Cisco IOS software
Note
The NSE-1 does not have packet SRAM.
System Management Functions
The NSE-1 performs the following system management functions:
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Sending and receiving routing protocol updates
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Managing tables, caches, and buffers
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Monitoring interface and environmental status
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Providing Simple Network Management Protocol (SNMP) management through the console and 
Telnet interface
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Accounting for and switching of data traffic 
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Booting and reloading images
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Managing port adapters (including recognition and initialization during online insertion and 
removal)
Terms and Acronyms
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Cache—Memory with fast access and small capacity used to temporarily store recently accessed 
data; found either incorporated into the processor or near it. 
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DIMM—dual in-line memory module
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DRAM—dynamic random-access memory
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Instruction and data cache—Instructions to the processor, and data on which the instructions work.
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Integrated cache—Cache that is built into the processor; sometimes referred to as internal cache. 
Cache memory physically located outside the processor is not integrated, and is sometimes referred 
to as external cache.
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OTP—one time programmable