SMSC LAN9420 Manual De Usuario
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
85
Revision 1.22 (09-25-08)
DATASHEET
4.1
Register Nomenclature
describes the register bit attributes used throughout this section.
Register attribute examples:
R/W: Can be written. Will return current setting on a read.
R/WC: Will return current setting on a read. Writing a one clears the bit.
Table 4.1 Register Bit Types
REGISTER BIT TYPE
NOTATION
REGISTER BIT DESCRIPTION
R
Read: A register or bit with this attribute can be read.
W
Write: A register or bit with this attribute can be written.
RO
Read only: Read only. Writes have no effect.
WO
Write only: If a register or bit is write-only, reads will return unspecified data.
WC
Write One to Clear: writing a one clears the value. Writing a zero has no effect
RC
Read to Clear: Contents is cleared after the read. Writes have no effect.
LL
Latch Low: This mode is used by the Ethernet PHY registers. Bits with this attribute
will stay low until the bit is read. After a read, the bit will remain low, but will change
to high if the condition that caused the bit to go low is removed. If the bit has not been
read the bit will remain low regardless of if its cause has been removed.
will stay low until the bit is read. After a read, the bit will remain low, but will change
to high if the condition that caused the bit to go low is removed. If the bit has not been
read the bit will remain low regardless of if its cause has been removed.
LH
Latch High: This mode is used by the Ethernet PHY registers. Bits with this attribute
will stay high until the bit is read. After a read, the bit will remain high, but will change
to low if the condition that caused the bit to go high is removed. If the bit has not been
read the bit will remain high regardless of if its cause has been removed.
will stay high until the bit is read. After a read, the bit will remain high, but will change
to low if the condition that caused the bit to go high is removed. If the bit has not been
read the bit will remain high regardless of if its cause has been removed.
SC
Self-Clearing: Contents is self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
effect. Contents can be read.
NASR
Not Affected by Software Reset. The state of NASR bits does not change on asser-
tion of a software reset.
tion of a software reset.
RESERVED
Reserved Field: Certain bits within registers are listed as “RESERVED”. Unless
stated otherwise, these bits must be written with zero for future compatibility. The val-
ues of these bits are not guaranteed when read.
stated otherwise, these bits must be written with zero for future compatibility. The val-
ues of these bits are not guaranteed when read.
Reserved Address: Certain addresses with the device are listed as “RESERVED”.
Unless otherwise noted, do not read from or write to reserved addresses.
Unless otherwise noted, do not read from or write to reserved addresses.